Data Sheet ADV7623
Rev. D | Page 3 of 16
FUNCTIONAL BLOCK DIAGRAM
CH0
CH1
CH2
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
08302-001
XTAL
XTAL1
RXA_C
RXB_C
RXC_C
RXD_C
RXA_0
RXA_1
RXA_2
VIDEO/AUDIO
CLOCK
GENERATION
RX
PLL
CEC
TXC
TX0
TX1
TX2
5V DETECT
COMPONENT
PROCESSOR
SCL
SDATA
ALSB
CS
I
2
C
CONTROLLER
PWRDN
RESET
GLOBAL
CONTROLS
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
AP0_IN
AP1_IN
AP2_IN
AP3_IN
AP4_IN
AP5_IN
SCLK_IN
MCLK_IN
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
AP5_OUT
SCLK_OUT
MCLK_OUT
ARC+
RX EDID/
REPEATER
CONTROLLER
RX HPD
CONTROLLER
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SPI MASTER/
SLAVE
EQUALIZER
RXB_0
RXB_1
RXB_2
EQUALIZER
SAMPLER
SAMPLER
RXC_0
RXC_1
RXC_2
EQUALIZER
SAMPLER
RXD_0
RXD_1
RXD_2
EQUALIZER
CEC
CONTROLLER
EDID
RAM
SAMPLER
HDMI RECEIVER
PROCESSOR
TRANSMITTER
PACKET BUILDER
HDCP
ENCRYPTION
ENGINE
HDMI
ENCODER
SERIALIZER
TMDS DRIVERS
INT1
INT2
INT_TX
INTERRUPT
CONTROLLER
TXDDC_SDA
TXDDC_SCL
TX
EDID/HDCP
CONTROLLER
EDID/HDCP
BUFFER
HPD_ARC–
TX HPD
CONTROLLER
HDCP
DECRYPTION
ENGINE
SYNC
MEASUREMENT
PACKET
PROCESSOR
INFOFRAME
PACKET
MEMORY
AUDIO
PROCESSOR
ARC
RECEIVER
AUDIO
CAPTURE
HDCP KEYS
TX
PLL
ADV7623
5V_DETA
5V_DETB
5V_DETC
5V_DETD
HP_CTRLA
HP_CTRLB
HP_CTRLC
HP_CTRLD
OSD
Figure 1.
ADV7623 Data Sheet
Rev. D | Page 4 of 16
SPECIFICATIONS
CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, TXAVDD = 1.8 V ± 5%,
TXPVDD = 1.8 V ± 5%, TXPLVDD = 1.8 V ± 5%, T
MIN
to T
MAX
= 0°C to 70°C.
DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS
Input High Voltage (V
IH
) 2 V
Input Low Voltage (V
IL
) 0.8 V
Input Current (I
IN
)
RESET
, EP_MISO, ALSB and
CS
pins −60 +60 µA
Other digital inputs −10 +10 µA
Input Capacitance (C
IN
) 10 pF
DIGITAL INPUTS (5 V TOLERANT)
1
Input High Voltage (V
IH
)
2.6 V
Input Low Voltage (V
IL
)
0.8 V
Input Current (I
IN
) −82 +82 µA
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
2.4 V
Output Low Voltage (V
OL
) 0.4 V
LEAK
10
µA
Output Capacitance (C
OUT
) 20 pF
HDMI
0.3
pF
AC SPECIFICATIONS
Input Specifications
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
0.4 t
BIT
ps
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
0.15 t
BIT
+ 112 ps
Channel-to-Channel Differential Input Skew 0.2 t
PIXEL
+ 1.78 ns
TMDS Input Clock Range 25 225 MHz
TMDS Input Clock Jitter Tolerance 0.5 0.25 t
BIT
Output Specifications
TMDS Output Clock Frequency 20 225 MHz
TMDS Output Clock Duty Cycle 48 52 %
TMDS Output Differential Swing 900 1100 1200 mV
Low-to-High Transition Time 75 175 ps
High-to-Low Transition Time 75 175 ps
1
The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL,
HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD,
PWRDN
, CEC, ARC+.
Data Sheet ADV7623
Rev. D | Page 5 of 16
DATA AND I
2
C TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VIDEO SYSTEM CLOCK AND XTAL
Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
External Clock Source
1
External crystal must operate at 1.8 V
Input High Voltage V
IH
XTAL driven with external clock source 1.2 V
Input Low Voltage V
IL
XTAL driven with external clock source 0.4 V
RESET FEATURE
Reset Pulse Width 5 ms
I
2
C PORTS (FAST MODE)
xCL Frequency
2
400 kHz
xCL Minimum Pulse Width High
2
t
1
600 ns
xCL Minimum Pulse Width Low
2
t
2
1.3
µs
Hold Time (Start Condition) t
3
600 ns
Setup Time (Start Condition) t
4
600 ns
xDA Setup Time
2
t
5
100 ns
xCL and xDA Rise Time
2
t
6
300 ns
xCL and xDA Fall Time
2
t
7
300 ns
Setup Time (Stop Condition) t
8
0.6 µs
I
2
C PORTS (NORMAL MODE)
xCL Frequency
2
100 kHz
xCL Minimum Pulse Width High
2
t
1
4.0 µs
xCL Minimum Pulse Width Low
2
t
2
4.7 µs
Hold Time (Start Condition) t
3
4.0 µs
Setup Time (Start Condition) t
4
4.7 µs
xDA Setup Time
2
t
5
250 ns
xCL and xDA Rise Time
2
t
6
1000
ns
xCL and xDA Fall Time
2
t
7
300 ns
Setup Time (Stop Condition) t
8
4.0 µs
AUDIO OUTPUT PORT (MASTER MODE)
SCLK Mark Space Ratio t
13
:t
14
45:55 55:45 % duty
cycle
APx_OUT Data Transition Time (LRCLK)
3
t
15
End of valid data to negative SCLK edge 10 ns
APx_OUT Data Transition Time (LRCLK)
3
t
16
Negative SCLK edge to start of valid data 10 ns
APx_OUT Data Transition Time (I
2
S Data)
3
t
17
End of valid data to negative SCLK edge 5 ns
APx_OUT Data Transition Time (I
2
S Data)
3
t
18
Negative SCLK edge to start of valid data 5 ns
AUDIO INPUT PORT
APx_IN Setup Time (I
2
S Data)
3
t
19
2
ns
APx_IN Hold Time (I
2
S Data)
3
t
20
2 ns
APx_IN Setup Time (LRCLK)
3
t
19
2 ns
APx_IN Hold Time (LRCLK)
3
t
20
2 ns
1
This part must be configured for external oscillator operation. A 1.8 V oscillator must be used.
2
The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3
The suffix x refers to 0, 1, 2, 3, 4, and 5.

ADV7623BSTZ-P-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC Require HDMI license see product comment
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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