Le79R241 Data Sheet
14
Zarlink Semiconductor Inc.
5.0 Electrical Characteristics
5.1 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device
reliability.
Notes:
1. Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165° C. Operation above 145° C junction
temperature may degrade device reliability.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance
requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through
multiple vias to a large internal copper plane.
2. Rise time of VBH (dv/dt) must be limited to less than 27 v/µs.
Storage temperature –55° to +150° C
Ambient temperature, under bias –40° to +85° C
Humidity 5% to 95%
VCC with respect to GND –0.4 to +7 V
VBH, VBL with respect to GND (see note 2) +0.4 to –104 V
BGND with respect to GND –3 to +3 V
Voltage on relay outputs +7 V
AD or BD to BGND:
Continuous VBH – 1 to BGND + 1
10 ms (F = 0.1 Hz) VBH – 5 to BGND + 5
1 µs (F = 0.1 Hz) VBH – 10 to BGND + 10
250 ns (F = 0.1 Hz) VBH – 15 to BGND + 15
Current into SA or SB:
10 µs rise to Ipeak
1000 µs fall to 0.5 Ipeak;
2000 µs fall to I =0
Ipeak = ±5 mA
Current into SA or SB:
2 µs rise to Ipeak
10 µs fall to 0.5 Ipeak;
20 µs fall to I = 0
Ipeak = ±12.5 mA
SA SB continuous 5 mA
Current through AD or BD ± 150 mA
P1, P2, P3, LD to GND –0.4 to VCC + 0.4 V
Maximum power dissipation (see note 1)
T
A
= 70° C
In 32-pin PLCC package
In 32-pin QFN package
T
A
= 85° C
In 32-pin PLCC package
In 32-pin QFN package
1.67 W
3.00 W
1.33 W
2.40 W
ESD Immunity (Human Body Model) JESD22 Class 1C compliant
