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M30281FATHP#U3A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
2. Central Processing Unit(CPU)
)B82/C61M,82/C61M(puorG82/C61M
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33fo6002,51.peS05.0.veR
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is
cleared to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write 0. When read, its content is indeterminate.
3. Memory
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)B82/C61M,82/C61M(puorG82/C61M
33fo6002,51.peS05.0.veR
3. Memory
Figure 3.1 is a memory map of the M16C/28 Group (M16C/28, M16C/28B). M16C/28 Group provides 1-
Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses
beginning with address FFFFF16. For example, 64 Kbytes internal ROM is allocated addresses F000016 to
FFFFF16.
Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version. The
blocks are allocated addresses F00016 to FFFF16.
The fixed interrupt vector tables are allocated addresses FFFDC16 to FFFFF16. It stores the starting ad-
dress of each interrupt routine. See the section on interrupts for details.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, 4-Kbytes
internal RAM is allocated addresses 0040016 to 013FF16. Besides storing data, it becomes stacks when the
subroutine is called or an interrupt is acknowledged.
SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O,
timers is allocated addresses 0000016 to 003FF16. All blank spaces within SFR are reserved and cannot be
accessed by users.
The special page vector table is allocated to the addresses FFE0016 to FFFDB16. This vector is used by the
JMPS or JSRS instruction. For details, refer to the
M16C/60 and M16C/20 Series Software Manual
.
Figure 3.1 Memory Map
00000
16
XXXXX
16
FFFFF
16
00400
16
YYYYY
16
Internal ROM Area
(program space)
SFR Area
Internal RAM Area
FFE00
16
FFFDC
16
FFFFF
16
Undefined Instruction
Overflow
BRK Instruction
Address Match
Single Step
Watchdog Timer
Reset
Special Page
Vector Table
DBC
RESERVED
Internal ROM Area
(data space)
RESERVED
0F000
16
XXXXX
16
YYYYY
16
Internal RAM area
Internal ROM area
Memory size
013FF
16
01AFF
16
F4000
16
F0000
16
4K bytes
6K bytes
48K bytes
64K bytes
Memory size
E8000
16
96K bytes
NOTES:
1. The block A (2K bytes) and block B (2K bytes) are shown (only flash memory).
2. Do not write to the internal ROM area in Mask ROM ver..
(1)
0FFFF
16
NMI
023FF
16
8K bytes
E0000
16
128K bytes
033FF
16
12K bytes
4. Special Function Register (SFR)
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33fo6002,51.peS05.0.veR
)B82/C61M,82/C61M(puorG82/C61M
4. Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR
information.
Table 4.1 SFR Information(1)
(1)
NOTES:
1.The blank spaces are reserved. No access is allowed.
2. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
3. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Undefined
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Address
Register Symbol After Reset
Processor mode register 0 PM0 0016
Processor mode register 1 PM1 000010002
System clock control register 0 CM0 010010002
System clock control register 1 CM1 001000002
Address match interrupt enable register AIER XXXXXX002
Protect register PRCR XX0000002
Oscillation stop detection register
(2)
CM2 0X0000102
Watchdog timer start register WDTS XX16
Watchdog timer control register WDC 00XXXXXX2
Address match interrupt register 0 RMAD0 0016
0016
X016
Address match interrupt register 1 RMAD1 0016
0016
X016
Voltage detection register 1
(3)
VCR1 000010002
Voltage detection register 2
(3)
VCR2 0016
PLL control register 0 PLC0 0001X0102
Processor mode register 2 PM2 XXX000002
Low voltage detection interrupt register D4INT 0016
DMA0 source pointer SAR0 XX16
XX16
XX16
DMA0 destination pointer DAR0 XX16
XX16
XX16
DMA0 transfer counter TCR0 XX16
XX16
DMA0 control register DM0CON 00000X002
DMA1 source pointer SAR1 XX16
XX16
XX16
DMA1 destination pointer DAR1 XX16
XX16
XX16
DMA1 transfer counter TCR1 XX16
XX16
DMA1 control register DM1CON 00000X002
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

M30281FATHP#U3A

Mfr. #:
Buy M30281FATHP#U3A
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 96K T-temp
Lifecycle:
New from this manufacturer.
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