Quick Start Guide AD9148(-M5372/5)-EBZ
Rev. A | Page 4 of 6
the desired tuning word. This will bypass the other control values on the left and directly write the FTW to the SPI.
Inverse Sinc Control
The AD9148 has a programmable Inverse Sinc filter.
The coefficients are ten 2’s complement numbers for
each of the two sets of DACs as described in the
datasheet. In order to program the coefficients using
the DAC software, the Bypass Inv Sinc control needs to
be set to the off position. The coefficients can either be
entered manually or generated from the DAC rate and
center frequencies of both DAC sets. Enter the
coefficients, in decimal form, into the blue boxes of
Figure 5 for manual setup. In order to use the built-in
coefficient calculator, enter the DAC rate and Center
Frequencies in the yellow boxes. Enable the Run
InvSinc Simulation control and run the software for the calculation of the coefficients.
Figure 5
PLL Control
The AD9148 has an on-chip PLL, with controls shown in Figure . In order
to ensure that the PLL will lock on the correct band using the auto-search
mode, the part must first be enabled in manual mode by selecting the
PLL_Enable and PLL Manual controls. From here, the part can be taken out
of manual mode by disabling the PLL Manual control. The PLL will start an
auto-search to determine the best band based on the Divider1 and Divider0
values selected. Included in this tab is the calculation for the DAC Freq and
VCO Freq based on the reference clock (Ref Clk control) and the value of
the dividers. The VCO Frequency must be between 1 and 2 GHz for proper
operation. The auto-band select can be bypassed by enabling PLL
MANUAL and entering a band in PLL Band Select. Divider1 and Divider0
must still be chosen appropriately in this mode of operation.
Figure 6
Interrupts
This tab provides a visual indication of the state of each interrupt. Enabling the button to the left of each interrupt with enable the
interrupt. A green indicator to the right of the button will light when the interrupt is asserted. Once asserted, the interrupt can be
acknowledged by pressing the Clear button.
Main DAC Control
This tab, shown in Figure , controls the four main DACs in the
AD9148. The Full-Scale Current of each DAC can be set with the
I[1/2] DAC Gain and Q[1/2] DAC Gain controls. The output current
setting is calculated and displayed for each DAC based on the
inputted code for the DAC Gains. The I[1/2] Sleep and Q[1/2] Sleep
controls put their respective DAC into a low-power sleep state.
When the AD9148 is used with a modulator, the phase compensation
(I/Q Phase Word) and DC offset controls (I/Q DC Offset Code) can
be used to correct any mismatches between the two DAC sets. Also
available are the I[1/2] Digital Gain and Q[1/2] Digital Gain which
scale the samples written to each individual DAC, yielding a
multiplier range of 0 to 3.984375.
Figure 7
