ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA 11
ICS9FG108E REV C 102912
SMBus Table: Reserved Register
Pin # Name Control Function T
e0 1Defaul
Bit 7
X
Bit 6
Bit 5
X
Bit 4
Bit 3
X
Bit 2
Bit 1
X
Bit 0
X
SMBus Table: Reserved Register
Pin # Name Control Function T
e0 1Defaul
Bit 7
Bit 6
X
Bit 5
Bit 4
X
Bit 3
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: M/N Programming Enable
Pin # Name Control Function T
e0 1Defaul
Bit 7
M/N_EN
PLL M/N Programming
Enable
RW Disable Enable 0
Bit 6
OE_Polarity
Select Polarity of OE
inputs
RW OE# OE
1
Bit 5
REFOUT_En
Enables/Disables REF RW Disable Enable
1
Bit 4
Bit 3
0
Bit 2
Bit 1
0
Bit 0
0
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function T
e0 1Defaul
Bit 7
PLL N Div8 N Divider Prog bit 8 RW X
Bit 6
PLL N Div9 N Divider Prog bit 9 RW X
Bit 5
Bit 4
PLL M Div4 RW X
Bit 3
Bit 2
PLL M Div2 RW X
Bit 1
PLL M Div1 RW X
Bit 0
PLL M Div0 RW X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B
te 8
Reserved
Reserved
B
te 7
Reserved
5
B
te 9
Reserved
B
te 10
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
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M Divider Programming
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