REV. B–12–
AD5516
A data transfer is initiated by writing a word to the TX Register
after the SPORT has been enabled. In write sequences, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5516 on the falling edge of its SCLK. The
SPORT transmit control register should be set up as follows:
DTYPE = 00, Right Justify Data
ICLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
INTF = 1, Internal Frame Sync
LTFS = 1, Active Low Frame Sync Signal
LAFS = 0, Early Frame Sync
SENDN = 0, Data Transmitted MSB First
SLEN = 10011, 18-Bit Data-Words (SLEN = Serial Word)
Figure 6 shows the connection diagram.
AD5516*
ADSP-2106x*
SYNC
D
IN
SCLK
TFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5516 to ADSP-2106x Interface
AD5516 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5516, the MOSI output drives the serial data line
(D
IN
) of the AD5516. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5516, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. In order to transmit 18 data bits, it is important to
left justify the data in the SPDR Register. PC7 must be pulled
low to start a transfer and taken high and low again before any
further read/write cycles can take place. A connection diagram is
shown in Figure 7.
AD5516*
MC68HC11*
SYNC
SCLK
D
IN
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD5516 to MC68HC11 Interface
AD5516 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit (CKP) = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In this
example, I/O port RA1 is being used to provide a SYNC signal
and enable the serial port of the AD5516. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, three consecutive write operations are required.
Figure 8 shows the connection diagram.
AD5516*
PIC16C6x/7x*
SCLK
D
IN
SYNC
SCK/RC3
SDI/RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD5516 to PIC16C6x/7x Interface
AD5516 to 8051
A serial interface between the AD5516 and the 80C51/80L51
microcontroller is shown in Figure 9. The AD5516 requires a
clock synchronized to the serial data. The 8051 serial interface
must therefore be operated in Mode 0. TxD of the microcon-
troller drives the SCLK of the AD5516, while RxD drives the
serial data line. P1.1 is a bit programmable pin on the serial port
that is used to drive SYNC. The 80C51/80L51 provides the
LSB first, while the AD5516 expects MSB of the 18-bit word
first. Care should be taken to ensure the transmit routine takes
this into account.
AD5516*
8051*
SCLK
D
IN
SYNC
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5516 to 8051 Interface
When data is to be transmitted to the DAC, P1.1 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the AD5516 clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As the DAC requires an 18-bit
word, P1.1 must be left low after the first eight bits are transferred
and brought high after the complete 18 bits have been transferred.
DOUT may be tied to RxD for data verification purposes when
the device is in Daisy-Chain Mode.
REV. B
AD5516
–13–
APPLICATION CIRCUITS
The AD5516 is suited for use in many applications, such as level
setting, optical, industrial systems, and automatic test applications.
In level setting and servo applications where a fine-tune adjust is
required, the Mode 2 function increases resolution. The following
figures show the AD5516 used in some potential applications.
AD5516 in a Typical ATE System
The AD5516 is ideally suited for the level setting function in
automatic test equipment. A number of DACs are required to
control pin drivers, comparators, active loads, parametric mea-
surement units, and signal timing. Figure 10 shows the AD5516
in such a system.
DAC
STORED
DATA AND
INHIBIT
PATTERN
PERIOD
GENERATION
AND
DELAY
TIMING
DACs
FORMATTER
COMPARE
REGISTER
SYSTEM BUS
DAC
DAC
DAC
DAC
ACTIVE
LOAD
PARAMETRIC
MEASUREMENT
UNIT
SYSTEM BUS
DAC
DAC
COMPARATOR
DUT
DRIVER
Figure 10. AD5516 in an ATE System
AD5516 in an Optical Network Control Loop
The AD5516 can be used in optical network control applica-
tions that require a large number of DACs to perform a control
and measurement function. In the example shown in Figure 11,
the outputs of the AD5516 are fed into amplifiers and used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is measured
and the readings are multiplexed into an 8-channel, 14-bit ADC
(AD7865). The increment and decrement modes of the DACs are
useful in this application as they allow 14-bit resolution.
The control loop is driven by an ADSP-2106x, a 32-bit
SHARC
®
DSP.
AD5516
0
15
MEMS
MIRROR
ARRAY
0
15
S
E
N
S
O
R
S
ADG609
2
0
7
AD7865
AD8644
2
ADSP-2106x
Figure 11. AD5516 in an Optical Control Loop
AD5516 in a High Current Circuit
Access to the feedback loop of the AD5516 amplifier provides
greater flexibility, e.g., it enables the user to configure the device
as a digitally programmable current source or increase the out-
put drive current. See Figure 12. Note that V
DD
must be chosen
so that the DAC output has enough headroom to drive the
BJT ~ 0.7 V above the maximum output voltage.
AD5516-1
V
DD
V
DAC
V
OUT
0
R
FB
0
R
V
x
= – 2.5V TO +2.5V
V
DD
V
SS
X
Figure 12. AD5516 in a High Current Circuit
Note it is not intended that the R
FB
nodes be used to alter
amplifier gain or for force/sense in remote sense applications.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the AD5516
is mounted should be designed so that the analog and digital
sections are separated and confined to certain areas of the board. If
the AD5516 is in a system where multiple devices require an
AGND-to-DGND connection, the connection should be made at
one point only. The star ground point should be established as
close as possible to the device. For supplies with multiple pins
(AV
CC
1, AV
CC
2), it is recommended to tie those pins together. The
AD5516 should have ample supply bypassing of 10 mF in parallel
with 0.1 mF on each supply located as closely to the package as
possible, ideally right up against the device. The 10 mF capacitors
are the tantalum bead type. The 0.1 mF capacitor should have low
effective series resistance (ESR) and effective series inductance
(ESI), like the common ceramic types that provide a low impedance
path to ground at high frequencies, to handle transient currents
due to internal logic switching.
The power supply lines of the AD5516 should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the D
IN
and
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane, but
separating the lines will help). It is essential to minimize noise
on REFIN.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
REV. B–14–
AD5516
OUTLINE DIMENSIONS
74-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-74)
Dimensions shown in millimeters
A
B
C
D
E
F
G
H
J
K
L
11 10 9 8 7 6 5 4 3 2 1
1.00
BSC
1.00 BSC
BOT TOM
VIEW
A1
TOP VIEW
DETAIL A
1.70
MAX
12.00 BSC
SQ
10.00 BSC
SQ
A1 CORNER
INDEX AREA
SEATING
PLANE
DETAIL A
BALL DIAMETER
0.30 MIN
0.70
0.60
0.50
0.20 MAX
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-192ABD-1

AD5516ABC-2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit Bipolar VTG- Output IC
Lifecycle:
New from this manufacturer.
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