OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD5516ABCZ-3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. B
AD5516
–3–
AC CHARACTERISTICS
(V
DD
= +4.75 V to +13.2 V, V
SS
= –4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.
All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
1, 2
A Version
3
Unit Conditions/Comments
Output Voltage Settling Time (Mode 1)
4
100 pF, 5 kW Load Full-Scale Change
AD5516–1 32 ␮s max
AD5516–2 32 ␮s max
AD5516–3 36 ␮s max
Output Voltage Settling Time (Mode 2)
4
100 pF, 5 kW Load, 127 Code Increment
AD5516–1 2.5 ␮s max
AD5516–2 3.35 ␮s max
AD5516–3 7 ␮s max
Slew Rate 0.85 V/␮s typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk
AD5516–1 1 nV-s typ
AD5516–2 5 nV-s typ
AD5516–3 20 nV-s typ
Digital Feedthrough 1 nV-s typ
Output Noise Spectral Density @ 10 kHz
AD5516–1 150 nV/(Hz)
1/2
typ
AD5516–2 350 nV/(Hz)
1/2
typ
AD5516–3 700 nV/(Hz)
1/2
typ
NOTES
1
See Terminology section.
2
Guaranteed by design and characterization; not production tested.
3
A version: Industrial temperature range –40∞C to +85∞C.
4
Timed from the end of a write sequence and includes BUSY low time.
Specifications subject to change without notice.
Limit at T
MIN
, T
MAX
Parameter
1, 2, 3
(A Version) Unit Conditions/Comments
f
UPDATE1
32 kHz max DAC Update Rate (Mode 1)
f
UPDATE2
750 kHz max DAC Update Rate (Mode 2)
f
CLKIN
20 MHz max SCLK Frequency
t
1
20 ns min SCLK High Pulsewidth
t
2
20 ns min SCLK Low Pulsewidth
t
3
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
5 ns min D
IN
Setup Time
t
5
5 ns min D
IN
Hold Time
t
6
0 ns min SCLK Falling Edge to SYNC Rising Edge
t
7
10 ns min Minimum SYNC High Time (Standalone Mode)
t
7MODE2
400 ns min Minimum SYNC High Time (Daisy-Chain Mode)
t
8MODE1
10 ns min BUSY Rising Edge to SYNC Falling Edge
t
9MODE2
200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
t
10
10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
t
11
4
20 ns max SCLK Rising Edge to D
OUT
Valid (Daisy-Chain Mode)
t
12
20 ns min RESET Pulsewidth
NOTES
1
See Timing Diagrams in Figures 1 and 2.
2
Guaranteed by design and characterization; not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
4
This is measured with the load circuit of Figure 3.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(V
DD
= +4.75 V to +13.2 V, V
SS
= – 4.75 V to –13.2 V; AV
CC
= 4.75 V to 5.25 V; DV
CC
= 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
REV. B–4–
AD5516
TIMING DIAGRAMS
t
12
SCLK
SYNC
DIN
BUSY
RESET
12 1718
t
3
t
7
t
4
t
5
t
2
t
1
t
6
t
9
MODE2
t
8
MODE1
BIT 17 BIT 0
LSBMSB
Figure 1. Serial Interface Timing Diagram
SCLK
SYNC
D
IN
D
OUT
BUSY
BIT 17 BIT 0 BIT 17 BIT 0
INPUT WORD FOR DEVICE N+1
UNDEFINED INPUT WORD FOR DEVICE N
INPUT WORD FOR DEVICE N
BIT 17 BIT 0
t
7
MODE2
t
3
t
2
t
1
t
6
t
10
t
5
t
4
t
11
t
8
MODE1
LSBMSB
Figure 2. Daisy-Chaining Timing Diagram
TO OUTPUT
PIN
C
L
50pF
200␮A
I
OH
200␮A
I
OL
1.6V
Figure 3. Load Circuit for D
OUT
Timing Specifications
REV. B
AD5516
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
AV
CC
to AGND, DACGND . . . . . . . . . . . . . . .–0.3 V to +7 V
DV
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to DV
CC
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to DV
CC
+ 0.3 V
REF_IN to AGND, DACGND . . . . . . –0.3 V to AV
CC
+ 0.3 V
V
OUT
0–15 to AGND . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
R
FB
0–15 to AGND . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+0.3 V
Operating Temperature Range, Industrial . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
MAX
) . . . . . . . . . . . . . . . . . . . 150°C
74-Lead CSPBGA Package, ␪
JA
Thermal Impedance . . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model Function Output Voltage Span Package Option
AD5516ABC-1 16 DACs ± 2.5 V 74-Lead CSPBGA
AD5516ABC-2 16 DACs ± 5 V 74-Lead CSPBGA
AD5516ABC-3 16 DACs ± 10 V 74-Lead CSPBGA
EVAL-AD5516-1EB Evaluation Board
EVAL-AD5516-2EB Evaluation Board
EVAL-AD5516-3EB Evaluation Board
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD5516ABCZ-3

Mfr. #:
Buy AD5516ABCZ-3
Manufacturer:
Description:
Digital to Analog Converters - DAC 12-Bit Bipolar VTG- Output IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet