Document Number: 001-06435 Rev. *J Page 8 of 17
AC Electrical Characteristics
Parameter
[5, 6]
Description
–15
Unit
Min Max
t
RC
Read cycle time 15 – ns
t
AA
Address to data valid – 15 ns
t
OHA
Data hold from address change 3 – ns
t
ACE
CE to data valid – 15 ns
t
DOE
OE to data valid – 7 ns
t
LZOE
OE to Low-Z
[7]
0 – ns
t
HZOE
OE to High-Z
[7, 8]
– 7 ns
t
LZCE
CE to Low-Z
[7]
3 – ns
t
HZCE
CE to High-Z
[7, 8]
– 7 ns
t
PU
CE to Power-up 0 – ns
t
PD
CE to Power-down – 15 ns
t
WC
Write Cycle Time
[9]
15 – ns
t
SCE
CE to write end 10 – ns
t
AW
Address setup to write end 10 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 9 – ns
t
SD
Data setup to write end 9 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to High-Z
[7, 8]
– 7 ns
t
LZWE
WE HIGH to Low-Z
[7]
3 – ns
Notes
5. Test Conditions are based on a transition time of 3 ns or less and timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
6. The minimum write cycle pulse width for Write Cycle No. 3 (WE
Controlled, OE LOW) should be equal to sum of t
SD
and t
HZWE
.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZCE
, t
HZWE
are specified as in part (b) of the Figure 1 on page 6. Transitions are measured ± 200 mV from steady state voltage.
9. The internal memory write time is defined by the overlap of CE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write.
