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MC74HC574ADTR2

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 15
1 Publication Order Number:
MC74HC574A/D
MC74HC574A
Octal 3-State Noninverting
D Flip-Flop
High−Performance Silicon−Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
DATA
INPUTS
D0
219
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
PIN 20 = V
CC
PIN 10 = GND
http://onsemi.com
20
11
20
MARKING DIAGRAMS
SOIC−20
HC574A
AWLYYWWG
HC
574A
ALYWG
G
TSSOP−20
SOEIAJ−20
74HC574A
AWLYWWG
20
1
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
F SUFFIX
CASE 967
FUNCTION TABLE
Inputs Output
OE Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = Don’t Care
Z = High Impedance
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
CLOCK
Q7
Q6
Q5
Q4
PIN ASSIGNMENT
MC74HC574A
http://onsemi.com
2
Design Criteria
Value Units
Internal Gate Count* 66.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product 0.0075 pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
I
DC Input Voltage −0.5 to V
CC
+ 0.5 V
V
O
DC Output Voltage (Note 1) −0.5 to V
CC
+ 0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±35 mA
I
O
DC Output Sink Current ±35 mA
I
CC
DC Supply Current per Supply Pin ±75 mA
I
GND
DC Ground Current per Ground Pin ±75 mA
T
STG
Storage Temperature Range −65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature under Bias +150
_C
q
JA
Thermal Resistance SOIC
TSSOP
96
128
_C/W
P
D
Power Dissipation in Still Air at 85_C SOIC
TSSOP
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 4000
> 300
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 5)
±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
I
, V
O
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 2) V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
MC74HC574A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Test Conditions
−55 to 25_C ≤ 85_C ≤ 125_C
Unit
V
IH
Minimum High−Level Input
Voltage
V
out
= V
CC
– 0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
| ≤ 2.4 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
| ≤ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IL
|I
out
| ≤ 2.4 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4.0 40 160
mA
P1-P3P4-P6P7-P9

MC74HC574ADTR2

Mfr. #:
Buy MC74HC574ADTR2
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-6V CMOS Octal
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