ISL9008AIRUNZ-T

7
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June 27, 2014
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Pin Description
FIGURE 15. LOAD TRANSIENT RESPONSE FIGURE 16. PSRR vs FREQUENCY
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
Typical Performance Curves (Continued)
1.0 ms/DIV
V
O
(10mV/DIV)
I
LOAD
100mA
100A
V
IN
= 3.8V
V
O
= 3.3V
0.1k 1k 10k 100k 1M
FREQUENCY (Hz)
10
20
30
40
50
60
80
PSRR (dB)
V
IN
= 3.9V
V
O
= 1.8V
C
LOAD
= 1µF
50mA
10mA
70
SPECTRAL NOISE DENSITY (V/Hz)
2.000
1.000
0.100
0.010
0.001
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
V
IN
= 3.9V
V
O
= 1.8V
C
IN
= 1µF
C
LOAD
= 1µF
100µA
10mA
5 LD SC-70
PIN NUMBER
6 LD µTDFN
PIN NUMBER PIN NAME DESCRIPTION
5 1 VO LDO Output. Connect a 1µF capacitor of value to GND
2 2 GND GND is the connection to system ground. Connect to PCB Ground plane.
4 3 and 5 NC No connect.
3 4 EN Output Enable. When this signal goes high, the LDO is turned on.
1 6 VIN Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
ISL9008A
8
FN6300.5
June 27, 2014
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Typical Application
Block Diagram
C1, C2: 1µF X5R CERAMIC CAPACITOR
ISL9008A
VIN
GND
VO
NC
5
4
1
2
V
IN
(2.3 TO 5V)
V
OUT
C1
C2
EN
3
ENABLE
OFF
ON
C1, C2: 1µF X5R CERAMIC CAPACITOR
ISL9008A (µTDFN)
VO
GND
VIN
EN
5
4
1
2
VOUT
C1
C2
NC
3
ENABLE
OFF
ON
NC
VIN (2.3 TO 5V)
6
VO
GND
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VIN
SHORT CIRCUIT,
THERMAL PROTECTION,
SOFT-START
SD
CONTROL
LOGIC
VOLTAGE AND
REFERENCE
GENERATOR
1.0V
0.94V
0.9V
GND
+
-
ISL9008A
9
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June 27, 2014
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Functional Description
The ISL9008A contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9008A adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart Thermal
shutdown protects the device against overheating. Soft-start
minimizes start-up input current surges without causing
excessive device turn-on time.
Power Control
The ISL9008A has an enable pin, EN, to control power to the
LDO output. When EN is low, the device is in shutdown
mode. In this condition, all on-chip circuits are off, and the
device draws minimum current, typically less than 0.3µA.
When the EN pin goes high, the device first polls the output
of the UVLO detector to ensure that the VIN voltage is at
least 2.1V (typical). Once verified, the device initiates a start-
up sequence. During the start-up sequence, trim settings are
first read and latched. Then sequentially, the bandgap,
reference voltage and current generation circuitry turn on.
Once the references are stable, the LDO powers up.
During operation, whenever the V
IN
voltage drops below
about 1.84V, the ISL9008A immediately disables the LDO
output. When V
IN
rises back above 2.1V (assuming the EN
pin is high), the device reinitiates its start-up sequence and
LDO operation resumes automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter.
The bandgap generates a zero temperature coefficient (TC)
voltage for the regulator reference and other voltage
references required for current generation and
over-temperature detection.
A current generator provides references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9008A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 4.7µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mW. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9008A provides short-circuit protection by limiting the
output current to about 265mA (typ).
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, the LDO
momentarily shuts down until the die cools sufficiently. In the
overheat condition, if the LDO sources more than 50mA it
will be shut off. Once the die temperature falls back below
about +110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
Exposed Thermal Pad
The ISL9008A with µTDFN package has an exposed
thermal pad at the bottom side of the package. The PCB
layout should connect the exposed pad to some copper on
the component layer for a good thermal conductivity. Since
the copper area on the component layer is limited by the
surrounding pins of the package, it is more effective to use
some thermal vias to conduct the heat to other copper layers
if possible.
Electrically, the copper and vias connecting to the exposed
pad should be isolated from any other pin connection, they
are strictly for thermal enhancement purpose.
ISL9008A

ISL9008AIRUNZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators W/ANNEAL SINGLE LW NOISE HI 3 00V SC-7
Lifecycle:
New from this manufacturer.
Delivery:
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