FDMB506P

December 2005
2005 Fairchild Semiconductor Corporation FDMB506P Rev C2(W)
FDMB506P
P-Channel 1.8V Logic Level PowerTrench
MOSFET
General Description
This P-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench process that
has been especially tailored to minimize the on-state
resistance and yet maintain low gate charge for
superior switching performance. These devices are
well suited for portable electronics applications.
Applications
Load switch
DC/DC Conversion
Features
–6.8 A, –20V. R
DS(ON)
= 30 m @ V
GS
= –4.5V
R
DS(ON)
= 38 m @ V
GS
= –2.5V
R
DS(ON)
= 70 m @ V
GS
= –1.8V
Low profile – 0.8 mm maximum
Fast switching
RoHS compliant
Absolute Maximum Ratings T
A
=25
o
C unless otherwise noted
Symbol Parameter Ratings Units
V
DSS
Drain-Source Voltage –20 V
V
GSS
Gate-Source Voltage
±8
V
I
D
Drain Current – Continuous (Note 1a) –6.8 A
Pulsed 70
P
D
Power Dissipation
(Note 1a) 1.9
W
T
J
, T
STG
Operating and Storage Junction Temperature Range –55 to +150
°C
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1a) 65
°C/W
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1b) 208
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
506 FDMB506P 7’’ 8mm 3000 units
FDMB506P
MicroFET
3x1.9
GATE
SOURCE
GATE
SOURCE
4
3
2
1
5
6
7
8
G
D
D
D
S
D
D
D
PIN 1
FDMB506P Rev C2(W)
Electrical Characteristics T
A
= 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
V
GS
= 0 V, I
D
= –250 µA
–20 V
BVDSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= –250 µA, Referenced to 25°C
–13
mV/°C
I
DSS
Zero Gate Voltage Drain Current V
DS
= –16 V, V
GS
= 0 V –1
µA
I
GSS
Gate–Body Leakage V
GS
= ± 8 V, V
DS
= 0 V ±100 nA
On Characteristics (Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= –250 µA
–0.4 –0.7 –1.5 V
VGS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= –250 µA, Referenced to 25°C
3
mV/°C
R
DS(on)
Static Drain–Source
On–Resistance
V
GS
= –4.5 V, I
D
= –6.8 A
V
GS
= –2.5 V, I
D
= –2.5 A
V
GS
= –1.8 V, I
D
= –1.8 A
V
GS
= –4.5 V, I
D
= –6.8 A, T
J
=125°C
25
30
40
36
30
38
70
44
m
g
FS
Forward Transconductance V
DS
= –5 V, I
D
= –6.8 A 26 S
Dynamic Characteristics
C
iss
Input Capacitance 2216 2960 pF
C
oss
Output Capacitance 351 470 pF
C
rss
Reverse Transfer Capacitance
V
DS
= –10 V, V
GS
= 0 V,
f = 1.0 MHz
167 260 pF
Switching Characteristics (Note 2)
t
d(on)
Turn–On Delay Time 14 25 ns
t
r
Turn–On Rise Time 8 16 ns
t
d(off)
Turn–Off Delay Time 175 280 ns
t
f
Turn–Off Fall Time
V
DD
= –10 V, I
D
= –1 A,
V
GS
= –4.5 V, R
GEN
= 6
80 128 ns
Q
g
Total Gate Charge 21 30 nC
Q
gs
Gate–Source Charge 3.5 nC
Q
gd
Gate–Drain Charge
V
DS
= –10 V, I
D
= –6.8 A,
V
GS
= –4.5 V
4.5 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current 1.6 A
V
SD
Drain–Source Diode Forward
Voltage
V
GS
= 0 V, I
S
= –0.8 A(Note 2) –0.6 –1.2 V
t
rr
Diode Reverse Recovery Time 26 48 nS
Q
rr
Diode Reverse Recovery Charge
I
F
= –6.8 A,
d
iF
/d
t
= 100 A/µs
12 22 nC
Notes:
1. R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 65°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b) 208°C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDMB506P
FDMB506P Rev C2(W)
Dimensional Outline and Pad Layout
NOTES:
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION,
MO-229, DATED 11/2001.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
FDMB506P

FDMB506P

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET LOW VOLTAGE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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