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25
FB
COMP
R
COMP (up)
OTA
I
FB
V
COMP (REF )
V
REF
I
OTAlim
I
COMP
OTA out = 0 A
if FB =0 V
Figure 45. FB Pin Connection
Design Procedure
The design of an SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us follow
the steps:
V
in
min = 90 Vac or 127 Vdc once rectified, assuming a low
bulk ripple
V
in
max = 265 Vac or 375 Vdc
V
out
= 12 V
P
out
= 5 W
Operating mode is CCM
η = 0.8
1. The lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of
a large leakage inductance) or in normal operation
as shown in Figure 46. This condition sets the
maximum voltage that can be reflected during toff.
As a result, the Flyback voltage which is reflected
on the drain at the switch opening cannot be larger
than the input voltage. When selecting
components, you thus must adopt a turn ratio
which adheres to the following equation:
N @
ǒ
V
out
) V
f
Ǔ
t V
in,min
(eq. 2)
2. In our case, since we operate from a 127 V DC rail
while delivering 12 V, we can select a reflected
voltage of 120 V dc maximum. Therefore, the turn
ratio Np:Ns must be smaller than
V
reflect
V
out
) V
f
+
120
12 ) 0.5
+ 9.6orNp:Nst 9.6.
Here we choose N = 8 in this case. We will see later
on how it affects the calculation.
1.004M 1.011M 1.018M 1.025M 1.032M
50.0
50.0
150
250
350
> 0 !!
Figure 46. The Drain−Source Wave Shall Always be Positive
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26
Figure 47. Primary Inductance Current
Evolution in CCM
3. Lateral MOSFETs have a poorly doped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications, a
simple capacitor can also be used since
V
drain,max
+ V
in
) N @
ǒ
V
out
) V
f
Ǔ
) I
peak
@
L
f
C
tot
Ǹ
(eq. 3
)
where L
f
is the leakage inductance, C
tot
the total
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the N
P
:N
S
turn ratio, V
out
the output
voltage, V
f
the secondary diode forward drop and
finally, I
peak
the maximum peak current. Worse case
occurs when the SMPS is very close to regulation,
e.g. the V
out
target is almost reached and I
peak
is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at V
in
= 375 Vdc). This voltage is given by the RCD clamp
installed from the drain to the bulk voltage. We will
see how to calculate it later on.
4. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
d
max
+
N @
ǒ
V
out
@ V
f
Ǔ
N @
ǒ
V
out
@ V
f
Ǔ
) V
in,min
(eq. 4)
+
1
1 )
V
in,min
N@(V
out
@V
f
)
+ 0.44
5. To obtain the primary inductance, we have the
choice between two equations:
L +
ǒ
V
in
@ d
Ǔ
2
f
sw
@ K @ P
in
(eq. 5)
where K +
DI
L
I
Lavg
and defines the amount of ripple we want in CCM (see
Figure 47).
Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
Large K: approaching DCM where the RMS losses are
worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 6, a K factor of 1 (50% ripple), gives an
inductance of:
L +
(
127 @ 0.44
)
2
60k @ 1 @ 5
+ 10.04 mH
DI
L
+
V
in
@ d
L @ f
sw
+
127 @ 0.44
10.04m @ 60k
+ 92.8 mA peak to peak
The peak current can be evaluated to be:
I
peak
+
I
avg
d
)
DI
L
2
+
49.2 m
0.44
)
92.8 m
2
+ 158 mA
On I
L
, I
Lavg
can also be calculated:
I
Lavg
+ I
peak
*
DI
L
2
+ 158m *
92.8m
2
+ 111.6 mA
6. Based on the above numbers, we can now evaluate
the conduction losses:
I
d,rms
+ d @
ǒ
I
peak
2
* I
peak
@ DI
L
)
DI
L
2
3
Ǔ
Ǹ
+ 0.44 @
ǒ
0.158
2
* 0.158 @ 0.0928 )
0.0928
2
3
Ǔ
Ǹ
+ 57 mA
If we take the maximum R
DS(on)
for a 125°C
junction temperature, i.e. 34 W, then conduction
losses worse case are:
P
cond
+ I
d,rms
2
@ R
DS(on)
+ 110 mW
7. Off−time and on−time switching losses can be
estimated based on the following calculations:
P
off
+
I
peak
@
ǒ
V
bulk
) V
clamp
Ǔ
@ t
off
2T
SW
+
0.158 @
(
127 ) 100 @ 2
)
@ 10n
2 @ 16.7 m
+ 15.5 mW
(eq. 6)
Where, assume the V
clamp
is equal to 2 times of reflected
voltage.
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27
P
on
+
I
valley
@
ǒ
V
bulk
) N @ (V
out
) V
f
)
Ǔ
@ t
on
6 @ T
SW
+
0.0464 @ (127 ) 100) @ 10 n
6 @ 16.7 m
+ 2.1 mW
(eq. 7)
It is noted that the overlap of voltage and current seen on
MOSFET during turning on and off duration is dependent on
the snubber and parasitic capacitance seen from drain pin.
Therefore the t
off
and t
on
in Equation 7 and Equation 8 have
to be modified after measuring on the bench.
8. The theoretical total power is then
117 + 15.5 + 2.1 = 127.6 mW
9. If the NCP106X operates at DSS mode, then the
losses caused by DSS mode should be counted as
losses of this device on the following calculation:
P
DSS
+ I
CC1
@ V
in.max
+ 0.8m @ 375 + 300 mW
(eq. 8)
MOSFET Protection
As in any Flyback design, it is important to limit the drain
excursion to a safe value, e.g. below the MOSFET BVdss
which is 700 V. Figure 48 a−b−c present possible
implementations:
Figure 48. a, b, c : Different Options to Clamp the Leakage Spike
Figure 48a: the simple capacitor limits the voltage
according to the lateral MOSFET body−diode shall never be
forward biased, either during start−up (because of a large
leakage inductance) or in normal operation as shown by
Figure 46. This condition sets the maximum voltage that can
be reflected during t
off
. As a result, the flyback voltage
which is reflected on the drain at the switch opening cannot
be larger than the input voltage. When selecting
components, you must adopt a turn ratio which adheres to
the following Equation 3. This option is only valid for low
power applications, e.g. below 5 W, otherwise chances exist
to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with (Equation 4). Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses...
Figure 48b: the most standard circuitry is called the RCD
network. You calculate R
clamp
and C
clamp
using the
following formulae:
R
clamp
+
2 @ V
clamp
@
ǒ
V
clamp
) N @ (V
out
) V
f
)
Ǔ
L
leak
@ I
leak
2
@ f
sw
(eq. 9)
C
clamp
+
V
clamp
V
ripple
@ f
sw
@ R
clamp
V
clamp
is usually selected 50−80 V above the reflected
value N x (V
out
+ V
f
). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. Worse case occurs when I
peak
and V
in
are maximum
and V
out
is close to reach the steady−state value.
Figure 48c: this option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a zener
diode or a TVS. There are little technology differences
behind a standard zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of zener.
A 5 W zener diode like the 1N5388B will accept 180 W peak
power if it lasts less than 8.3 ms. If the peak current in the
worse case (e.g. when the PWM circuit maximum current
limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5 W of continuous power
but is able to accept surges up to 600 W @ 1 ms. Select the
zener or TVS clamping level between 40 to 80 volts above the
reflected output voltage when the supply is heavily loaded.
As a good design practice, it is recommended to
implement one of this protection to make sure Drain pin
voltage doesn’t go above 650 V (to have some margin
between Drain pin voltage and BVdss) during most stringent
operating conditions (high Vin and peak power).

NCP1060AD060R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HV SWITCHER FOR LOW
Lifecycle:
New from this manufacturer.
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