5
FN3369.5
April 25, 2013
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(Q
N6
and Q
P6
) to set up the base voltage on Q
P5
.
Q
P5
begins to conduct whenever the high impedance node
reaches a voltage equal to Q
P5
’s base + 2V
BE
(Q
P5
and
Q
N5
). Thus, Q
P5
clamps node Z whenever Z reaches V
H
.
R
1
provides a pull-up network to ensure functionality with the
clamp inputs floating. A similar description applies to the
symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. Q
P5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as (V
-IN
- V
OUT
)/R
F
. As
an example, a unity gain circuit with V
IN
= 2V, V
H
= 1V, and
R
F
= 510Ω would have I
CLAMP
= (2-1)/510Ω = 1.96mA.
Note that I
CC
will increase by I
CLAMP
when the output is
clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to V
H
or V
L
. Offset errors, mostly due to V
BE
mismatches, necessitate a clamp accuracy parameter which is
found in the device specifications. Clamp accuracy is a function
of the clamping conditions. Referring again to Figure 1, it can
be seen that one component of clamp accuracy is the V
BE
mismatch between the Q
X6
transistors, and the Q
X5
transistors. If the transistors always ran at the same current
level there would be no V
BE
mismatch, and no contribution to
the inaccuracy. The Q
X6
transistors are biased at a constant
current, but as described earlier, the current through Q
X5
is
equivalent to I
CLAMP
. V
BE
increases as I
CLAMP
increases,
causing the clamped output voltage to increase as well. I
CLAMP
is a function of the overdrive level (V
-IN
-V
OUTCLAMPED
) and
R
F
, so clamp accuracy degrades as the overdrive increases, or
as R
F
decreases. As an example, the specified accuracy of
±60mV for a 2X overdrive with R
F
= 510Ω degrades to ±220mV
for R
F
= 240Ω at the same overdrive, or to ±250mV for a 3X
overdrive with R
F
= 510Ω.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve in the data sheet
illustrates the impact of several clamp levels on linearity.
Clamp Range
Unlike some competitor devices, both V
H
and V
L
have usable
ranges that cross 0V. While V
H
must be more positive than V
L
,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HFA1130 could
be limited to ECL output levels by setting V
H
= -0.8V and
V
L
= -1.8V. V
H
and V
L
may be connected to the same voltage
(GND for instance) but the result won’t be in a DC output
voltage from an AC input signal. A 150 - 200mV AC signal will
still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (V
CLAMP
/A
VCL
) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1130’s
subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed.
Note: The propagation delay illustrated is dominated by the
fixturing. The delta shown is accurate, but the true HFA1130
propagation delay is 500ps.
Use of Die in Hybrid Applications
This amplifier is designed with compensation to negate the
package parasitics that typically lead to instabilities. As a
result, the use of die in hybrid applications results in
overcompensated performance due to lower parasitic
capacitances. Reducing R
F
below the recommended values
for packaged units will solve the problem. For A
V
= +2 the
recommended starting point is 300Ω, while unity gain
applications should try 400Ω.
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
chip (0.1μF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown below.
HFA1130
