LTC3548A
3
3548afa
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3548AE is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C and 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3548AI is guaranteed over the
full –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at T
J
= 25°C. V
IN
= 3.6V, unless otherwise specifi ed. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Operating Voltage Range
●
2.5 5.5 V
I
FB
Feedback Pin Input Current
●
30 nA
V
FB
Feedback Voltage (Note 3) 0°C ≤ T
A
≤ 85°C
–40°C ≤ T
A
≤ 125°C (Note 2) ●
0.588
0.585
0.6
0.6
0.612
0.612
V
V
ΔV
LINE REG
Reference Voltage Line Regulation V
IN
= 2.5V to 5.5V (Note 3) 0.3 0.5 %/V
ΔV
LOAD REG
Output Voltage Load Regulation MODE/SYNC = 0V (Note 3) 0.5 %
I
S
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
V
FB1
= V
FB2
= 0.5V
V
FB1
= V
FB2
= 0.63V, MODE/SYNC = 3.6V
RUN = 0V, V
IN
= 5.5V, MODE/SYNC = 0V
700
40
0.1
950
60
1
μA
μA
μA
f
OSC
Oscillator Frequency V
FBX
= 0.6V
●
1.8 2.25 2.7 MHz
f
SYNC
Synchronization Frequency 2.25 MHz
I
LIM
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
V
IN
= 3V, V
FBX
= 0.5V, Duty Cycle < 35%
V
IN
= 3V, V
FBX
= 0.5V, Duty Cycle < 35%
1
0.6
1.2
0.7
1.6
0.9
A
A
R
DS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
I
SW(LKG)
Switch Leakage Current V
IN
= 5V, V
RUN
= 0V, V
FBX
= 0V 0.01 1 μA
POR Power-On Reset Threshold V
FBX
Ramping Up, MODE/SYNC = 0V
V
FBX
Ramping Down, MODE/SYNC = 0V
8.5
–8.5
%
%
Power-On Reset On-Resistance 100 200 Ω
Power-On Reset Delay 65,536 Cycles
V
RUN
RUN/SS Threshold Low
RUN/SS Threshold High
●
●
0.3 1 1.5
2
V
V
I
RUN
RUN/SS Leakage Current
●
0.01 1 μA
V
MODE
MODE Threshold Low
MODE Threshold High
0
V
IN
– 0.5
0.5
V
IN
V
V
Note 3: The LTC3548A is tested in a proprietary test mode that connects
V
FB
to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient, T
A
, and power dissipation, P
D
,
according to the following formula:
T
J
= T
A
+ (P
D
• θ
JA
).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
