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557MI-01LF

P1-P3P4-P6P7-P9P10-P10
DATASHEET
PCI-EXPRESS GEN1 CLOCK SOURCE ICS557-01
IDT®
PCI-EXPRESS GEN1 CLOCK SOURCE 1
ICS557-01 REV P 072512
Description
The ICS557-01 is a clock chip designed for use in
PCI-Express Cards as a clock source. It provides a pair of
differential outputs at 100 MHz in a small 8-pin SOIC
package.
Using IDT’s patented Phase-Locked Loop (PLL)
techniques, the device takes a 25 MHz crystal input and
produces HCSL (Host Clock Signal Level) differential
outputs at 100 MHz clock frequency. LVDS signal levels can
also be supported via an alternative termination scheme.
Features
• Supports PCI-Express
TM
HCSL Outputs
0.7 V current mode differential pair
• Supports LVDS Output Levels
• Packaged in 8-pin SOIC
• RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
• Operating voltage of 3.3 V
• Low power consumption
• Input frequency of 25 MHz
• Short term jitter 100 ps (peak-to-peak)
• Output Enable via pin selection
• Industrial temperature range available
• For PCIe Gen2 applications, see the 5V41064
• For PCIe Gen3 applications, see the 5V41234
Block Diagram
Phase Lock
Loop
Clock
Buffer/
Crystal
Oscillator
VDD
GND
X2
25 MHz
crystal /clock
CLK
OE
CLK
R
R
(IREF)
X1
Crystal Tuning Capacitors
ICS557-01
PCI-EXPRESS GEN1 CLOCK SOURCE PCIE
IDT®
PCI-EXPRESS GEN1 CLOCK SOURCE 2
ICS557-01 REV P 072512
Pin Assignment
Pin Descriptions
1
2
3
X1
4
X2
VDD
IREF
GND
CLK
CLK
8
7
6
5
OE
8 Pin (150 mil) SOIC
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 OE Input Output Enable signal
(H = outputs are enabled, L = outputs are disabled/tristated).
Internal pull-up resistor.
2 X1 Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
3 X2 XO Crystal Connection. Connect to a parallel mode crystal.
Leave floating if clock input.
4 GND Power Connect to ground.
5 IREF Output A 475Ω precision resistor connected between this pin and ground
establishes the external reference current.
6 CLK Output HCSL differential complementary clock output.
7 CLK Output HCSL differential clock output.
8 VDD Power Connect to +3.3 V.
ICS557-01
PCI-EXPRESS GEN1 CLOCK SOURCE PCIE
IDT®
PCI-EXPRESS GEN1 CLOCK SOURCE 3
ICS557-01 REV P 072512
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01 μF should be connected
between VDD and the ground plane (pin 4) as close to the
VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into IDT pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with
C
L
= 16 pF should be used. This crystal must have less than
300 ppm of error across temperature in order for the
ICS557-01 to meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50Ω, then R
R
= 475Ω
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the ICS557-01
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-01can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout Guidelines
section
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-01.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
W
P1-P3P4-P6P7-P9P10-P10

557MI-01LF

Mfr. #:
Buy 557MI-01LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCI-EXPRESS CLOCK SOURCE
Lifecycle:
New from this manufacturer.
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