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LTC3412EFE#PBF

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LTC3412
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Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, mollypermalloy,
or Kool Mμ
®
cores. Actual core loss is independent of core
size for a fixed inductor value but it is very dependent on
the inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for the
maximum RMS current should be used. RMS current is
given by:
II
V
V
V
V
RMS OUT MAX
OUT
IN
IN
OUT
= −
()
1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
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offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔV
OUT
, is determined by:
Δ≤Δ +
⎛
⎝
⎜
⎞
⎠
⎟
V I ESR
fC
OUT L
OUT
1
8
The output ripple is highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
LTC3412
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current to remain equal to I
BURST
regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the I
TH
pin will decrease. When the I
TH
voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
I
BURST
is determined by the desired amount of output
voltage ripple. As the value of I
BURST
increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, V
BURST
, can be set by a
resistor divider from the V
FB
pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
connecting the SYNC/MODE pin to ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still op-
erating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skipped while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external fre-
quency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (I
Q
< 1μA).
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the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
VV
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
08 1
2
1
.
The resistive divider allows the V
FB
pin to sense a fraction
of the output voltage as shown in Figure 2.
Figure 2. Setting the Output Voltage
LTC3412
V
FB
V
OUT
SGND
3412 F02
R2
R1
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V
IN
by 1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, I
BURST
, for each switching cycle accord-
ing to the following equation:
IV V
A
V
BURST BURST
= −
()
⎛
⎝
⎜
⎞
⎠
⎟
02
375
08
.
.
.
V
BURST
is the voltage on the SYNC/MODE pin. I
BURST
can
be programmed in the range of 0A to 3.75A. For values of
V
BURST
greater than 1V, I
BURST
is set at 3.75A. For values
of V
BURST
less than 0.2V, I
BURST
is set at 0A. As the output
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
BURST
, the burst clamp will force the peak inductor
LTC3412
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The LTC3412 contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
tRC
V
VV
Seconds
SS SS SS
IN
IN
=
−
⎛
⎝
⎜
⎞
⎠
⎟
()
ln
.18
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
=f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3412 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3412 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3412 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
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LTC3412EFE#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2.5A, 4MHz, Mono Sync Buck Reg
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