LTC3412
8
3412fb
OPERATIO
U
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOS-
FET is switched on until either the overvoltage condition
clears or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SV
IN
will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage between 0V
to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I
TH
pin drops. As the I
TH
voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top MOSFET is held
off and the I
TH
pin is disconnected from the output of the
error amplifier. The majority of the internal circuitry is also
turned off to reduce the quiescent current to 62μA while
the load current is solely supplied by the output capacitor.
When the output voltage drops, the I
TH
pin is reconnected
to the output of the error amplifier and the top power
MOSFET along with all the internal circuitry is switched
back on. This process repeats at a rate that is dependent
on the load demand.
Pulse skipping operation can be implemented by connect-
ing the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
the I
TH
pin until the I
TH
voltage drops below 200mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3412 can be synchronized
to an external clock connected to the SYNC/MODE pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V and
each switching cycle begins at the falling edge of the
external clock signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412 is designed to operate down to an input
supply voltage of 2.625V. One important consideration at
low input supply voltages is that the R
DS(ON)
of the P-
channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
