CS8130-CS Datasheet CDB8130, CS8130-CS, CS8130-CSZ | P19-P21

Register 16, TV Remote Receive Timing Register #1

D3 D2 D1 D0

TVR3 TVR2 TVR1 TVR0

1111

Register

Reset (R)

BIT NAME VALUE FUNCTION

TVR11-0 TV remote mode

receiver timing

register

TVR = (3.6864E6 *

T) -1

where T = the

incoming bit period,

and TVR = this

register value.

000000000000

000000000001

↓

011111111111

↓

111111111111

0

1

↓

2047R

↓

4095

T = 271 ns

T = 542 ns

↓

T = 555 µs (1800 bps)

↓

T = 1.11 ms

For TV remote receive "oversampled" mode, this register value determines the input data sample rate.

The sample rate is 3.6864 MHz divided by this register value. The sample rate should be set to as fast

as possible, to give the best resolution on the incoming data edges, but should be less than 80% of the

main UART communication baud rate.

For TV remote receive "programmed T period" mode, this register sets the expected incoming bit cell

time (T). The main UART communications rate must be set to at least 20% greater than 1/T.

Register 17, TV Remote Receive Timing Register #2

D3 D2 D1 D0

TVR7 TVR6 TVR5 TVR4

1111

Register

Reset (R)

Register 18, TV Remote Receive Timing Register #3

D3 D2 D1 D0

TVR11 TVR10 TVR9 TVR8

0111

Register

Reset (R)

CS8130

DS134PP2 19

CS8130

DS134F1 19

Register 19, TV Remote Transmit Bit Rate Divider Register #1

D3 D2 D1 D0

TBR3 TBR2 TBR1 TBR0

1111

Register

Reset (R)

BIT NAME VALUE FUNCTION

TBR7-0 TV remote mode

transmit bit rate

register

TBR=

(3.6864E6/(16*RATE))

-1

where TBR is this

register value &

RATE is the desired

transmit bit rate.

01111111 127 R RATE = 1800 bps

Register 20, TV Remote Transmit Bit Rate Divider Register #2

D3 D2 D1 D0

TBR7 TBR6 TBR5 TBR4

0111

Register

Reset (R)

Register 21, Control Register #4

D3 D2 D1 D0

OSCE OSCL EXCK SRES

0000

Register

Reset (R)

BIT NAME VALUE FUNCTION

OSCE Disable crystal

oscillator in D/

C

controlled

power down state

0

1

RIn D/

C controlled power down state, crystal

oscillator stays running.

In D/

C controlled power down state, crystal

oscillator stops.

OSCL Set oscillator in low

power mode

0

1

R Oscillator in normal power, high accuracy, mode.

Oscillator in low power, medium accuracy mode.

EXCK Disable external

clock output driver

0

1

R If crystal is used, enable clock output driver

If crystal is used, disable clock output driver (Hi-Z)

SRES Software Reset 0

1

R Normal operation

Causes a software reset, which forces all registers

into their reset state. If ECHO is true, then the echo

will occur at the current baud rate, before the baud

rate changes to the default value.

CS8130

20 DS134PP2

CS8130

20 DS134F1

Register 28, CS8130 Silicon Revision Register

D3 D2 D1 D0

REV3 REV2 REV1 REV0

Register

BIT NAME VALUE FUNCTION

REV3-0 CS8130 silicon

revision level

0000 1st silicon, designed to meet DS134PP2 data sheet,

dated June 1994

This register should be read by the CS8130 driver to allow CS8130 future enhancements to be recog-

nized, and incorporated into future versions of the driver.

Register 24, Receive ASK Timing Sensitivity Register

D3 D2 D1 D0

RAT3 RAT2 RAT1 RAT0

0000

Register

Reset (R)

BIT NAME VALUE FUNCTION

RAT3-0 Receiver ASK

Timing Sensitivity.

Timing window =

+0.27 µs to

-RAT(2/3.6864E06)

- 0.27 µs

0000

0001

0010

↓

1111

0R

1

2

↓

15

+0.27 µs to -0.27 µs window (500 kHz ASK mode)

+0.27 µs to -0.54 - 0.27 µs window

+0.27 µs to -1.08 - 0.27 µs window

↓

+0.27 µs to -8.14 - 0.27 µs window

The timing window is relative to the modulation divider register nominal setting.

CS8130

DS134PP2 21

CS8130

DS134F1 21

CS8130-CS

CS8130-CS

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