MAX5304
10-Bit Voltage-Output DAC
in 8-Pin µMAX
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In shutdown mode, the amplifier’s output and the refer-
ence input enter a high-impedance state. The serial
interface remains active. Data in the input register is
retained in shutdown, allowing the MAX5304 to recall
the output state prior to entering shutdown. Exit shut-
down mode by either recalling the previous configura-
tion or updating the DAC with new data. When
powering up the device or bringing it out of shutdown,
allow 20µs for the outputs to stabilize.
Serial-Interface Configurations
The MAX5304’s 3-wire serial interface is compatible
with MICROWIRE (Figure 2) and SPI/QSPI (Figure 3).
The serial-input word consists of three control bits fol-
lowed by 10+3 data bits (MSB first), as shown in Figure
4. The 3-bit control code determines the MAX5304’s
response outlined in Table 1.
The MAX5304’s digital inputs are double buffered.
Depending on the command issued through the serial
interface, the input register can be loaded without
affecting the DAC register, the DAC register can be
loaded directly, or the DAC register can be updated
from the input register (Table 1).
Serial-Interface Description
The MAX5304 requires 16 bits of serial data. Table 1
lists the serial-interface programming commands. For
certain commands, the 10+3 data bits are “don’t
cares.” Data is sent MSB first and can be sent in two 8-
bit packets or one 16-bit word (CS must remain low
until 16 bits are transferred). The serial data is com-
posed of three control bits (C2, C1, C0), followed by
the 10+3 data bits D9...D0, S2, S1, S0 (Figure 4). Set
the sub-bits (S2, S1, S0) to zero. The 3-bit control code
determines the register to be updated and the configu-
ration when exiting shutdown.
Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
t
CSS
before the rising serial-clock (SCLK) edge to prop-
erly clock in the first bit. When CS is low, data is
clocked into the internal shift register through the serial-
data input pin (DIN) on SCLK’s rising edge. The maxi-
mum guaranteed clock frequency is 10MHz. Data is
latched into the MAX5304 input/DAC register on CS’s
rising edge.
