16 Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00B
12/22/08
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Symbol Parameter Test Condition –6 –7 Unit
I
d d 1
(1)
Operating Current One Bank Active, CL = 3, BL = 1,
tclK = tCLK(min), tRC = tRC(min)
90 85 mA
I
d d 2p
(4)
Precharge Standby Current
(In Power-Down Mode)
CKE V
i l (max), tCK = 15ns
CS V
d d - 0.2V
1 1 mA
I
d d 2p s
(4)
Precharge Standby Current
With Clock Stop
(In Power-Down Mode)
CKE V
i l (max), CLK Vi l (max)
CS V
d d - 0.2V
1 1 mA
I
d d 2n
(2)
Precharge Standby Current
(In Non Power-Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
tCK = 15 ns
35 35 mA
I
d d 2n s Precharge Standby Current
With Clock Stop
(In Non-Power Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
All Inputs Stable
20 20 mA
I
d d 3p
(2)
Active Standby Current
(In Power-Down Mode)
CKE Vi l (max), CS Vd d - 0.2V
tCK = 15 ns
2 2 mA
I
d d 3p s Active Standby Current
With Clock Stop
(In Power-Down Mode)
CKE V
i l (max), CLK Vi l (max)
CS V
d d - 0.2V
2 2 mA
I
d d 3n
(2)
Active Standby Current
(In Non Power-Down Mode)
CS Vd d - 0.2V, CKE Vi h (min)
tCK = 15 ns
40 40 mA
I
d d 3n s Active Standby Current
With Clock Stop
(In Non Power-Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
All Inputs Stable
25 25 mA
I
d d 4 Operating Current All Banks Active, BL =4, CL = 3
tCK = tCK(min)
120 110 mA
I
d d 5 Auto-Refresh Current tRC = tRC(min), tCLK = tCLK(min) 180 140 mA
I
d d 6 Self-Refresh Current CKE 0.2V 1.2 1.2 mA
I
d d 7 Self-Refresh: CKE = LOW; tCK = tCK (MIN);
Address, Control, and Data bus inputs are
stable
Full Array, 85
o
C
Full Array, 45
o
C
Half Array, 85
o
C
Half Array, 45
o
C
1/4th Array, 85
o
C
1/4th Array, 45
o
C
1/8th Array, 85
o
C
1/8th Array, 45
o
C
1/16th Array, 85
o
C
1/16th Array, 45
o
C
1200
900
1000
750
900
675
850
640
800
600
mA
I
z z
(3,4)
Deep Power Down Current CKE 0.2V 15 15 mA
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V/2.5V, x8 and x16
Notes:
1. I
d d (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. I
z z values shown are nominal at 25
o
C. Iz z is not tested.
4. Tested after 500ms delay.
Integrated Silicon Solution, Inc. - www.issi.com 17
Rev. 00B
12/22/08
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
Symbol Parameter Test Condition –6
5
–7 Unit
I
d d 1
(1)
Operating Current One Bank Active, CL = 3, BL = 1,
tclK = tCLK(min), tRC = tRC(min)
140 135 mA
I
d d 2p
(4)
Precharge Standby Current
(In Power-Down Mode)
CKE V
i l (max), tCK = 15ns
CS V
d d - 0.2V
1 1 mA
I
d d 2p s
(4)
Precharge Standby Current
With Clock Stop
(In Power-Down Mode)
CKE V
i l (max), CLK Vi l (max)
CS V
d d - 0.2V
1 1 mA
I
d d 2n
(2)
Precharge Standby Current
(In Non Power-Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
tCK = 15 ns
45 45 mA
I
d d 2n s Precharge Standby Current
With Clock Stop
(In Non-Power Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
All Inputs Stable
30 30 mA
I
d d 3p
(2)
Active Standby Current
(In Power-Down Mode)
CKE V
i l (max), CS Vd d - 0.2V
tCK = 15 ns
4 4 mA
I
d d 3p s Active Standby Current
With Clock Stop
(In Power-Down Mode)
CKE V
i l (max), CLK Vi l (max)
CS V
d d - 0.2V
3 3 mA
I
d d 3n
(2)
Active Standby Current
(In Non Power-Down Mode)
CS Vd d - 0.2V, CKE Vi h (min)
tCK = 15 ns
55 55 mA
I
d d 3n s Active Standby Current
With Clock Stop
(In Non Power-Down Mode)
CS V
d d - 0.2V, CKE Vi h (min)
All Inputs Stable
30 30 mA
I
d d 4 Operating Current All Banks Active, BL =4, CL = 3
tCK = tCK(min)
180 170 mA
I
d d 5 Auto-Refresh Current tRC = tRC(min), tCLK = tCLK(min) 180 170 mA
I
d d 6 Self-Refresh Current CKE 0.2V 1.2 1.2 mA
I
d d 7 Self-Refresh: CKE = LOW; tCK = tCK (MIN);
Address, Control, and Data bus inputs are
stable
Full Array, 85
o
C
Full Array, 45
o
C
Half Array, 85
o
C
Half Array, 45
o
C
1/4th Array, 85
o
C
1/4th Array, 45
o
C
1/8th Array, 85
o
C
1/8th Array, 45
o
C
1/16th Array, 85
o
C
1/16th Array, 45
o
C
1200
900
1000
750
900
675
850
640
800
600
mA
I
z z
(3,4)
Deep Power Down Current CKE 0.2V 15 15 mA
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V/2.5V, x32
Notes:
1. I
d d (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. I
z z values shown are nominal at 25
o
C. Iz z is not tested.
4. Tested after 500ms delay.
5. Not available for 2.5V, x32 option
18 Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00B
12/22/08
IS42SM81600E / IS42SM16800E / IS42SM32400E
IS42RM81600E / IS42RM16800E / IS42RM32400E
AC ELECTRICAL CHARACTERISTICS
(1, 2, 3)
-6
4
-7
Symbol Parameter Min. Max. Min. Max. Unit
tCK3
tCK2
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
6
10
7
10
ns
ns
tAC3
tAC2
Access Time From CLK
CAS Latency = 3
CAS Latency = 2
5.4
8
5.4
8
ns
ns
tCHI CLK HIGH Level Width 2.5 2.5 ns
tCL CLK LOW Level Width 2.5 2.5 ns
tOH3
tOH2
Output Data Hold Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
2.7
2.7
ns
ns
tLZ Output LOW Impedance Time 0 0 ns
tHZ Output HIGH Impedance Time
CAS Latency = 3
CAS Latency = 2
2.7
2.7
5.4
8
2.7
2.7
5.4
8
ns
tDS Input Data Setup Time
(2)
1.5 1.5 ns
tDH Input Data Hold Time
(2)
1.0 1.0 ns
tAS Address Setup Time
(2)
1.5 1.5 ns
tAH Address Hold Time
(2)
1.0 1.0 ns
tCKS CKE Setup Time
(2)
1.5 1.5 ns
tCKH CKE Hold Time
(2)
1.0 1.0 ns
tCS
Command Setup Time (CS,
RAS, CAS, WE, DQM)
(2)
1.5 1.5 ns
tCH
Command Hold Time (CS,
RAS, CAS, WE, DQM)
(2)
1.0 1.0 ns
tRC Command Period (REF to REF
/ ACT to ACT)
60 67.5 ns
tRAS Command Period (ACT to
PRE)
42 100K 45 100K ns
tRP Command Period (PRE to
ACT)
18 20 ns
tRCD Active Command to Read/
Write Command Delay Time
18 20 ns
tRRD Command Period (ACT [0] to
ACT [1])
12 14 ns
tDPL Input Data to Precharge 12 14 ns
Command Delay Time
tDAL Input Data to Active/Refresh
Command Delay Time (During
Auto-Precharge)
30 35 ns
tMRD Mode Register Program Time 12 14 ns
tDDE Power Down Exit Setup Time 6 7 ns
tSRX Self-Refresh Exit Time 70 70 ns
tT Transition Time 0.3 1.2 0.3 1.2 ns
tREF Refresh Cycle Time (4096) 64 64 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between
V
i h (min.) and Vi l (max).
4. Not available for 2.5V, x32 option.

IS42SM16800E-75ETLI

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 54TFBGA
Lifecycle:
New from this manufacturer.
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