HMC8108LC5 Datasheet HMC8108LC5, HMC8108LC5TR, HMC8108LC5TR-R5 | P4-P6

Data Sheet HMC8108

Rev. 0 | Page 3 of 18

SPECIFICATIONS

T

A

= −25°C, IF = 60 MHz, LNA_VD1/LNA_VD2 = +3 V, BU F F_VD = +3 V, VCTRL = −1 V, MIX_VG = −1.4 V, LO power= −5 dBm,

downconverter mode with lower side selected and external 90° hybrid at the IF ports, unless otherwise noted.

Table 1.

Parameter Symbol Min Typ Max Unit

OPERATING CONDITIONS

Frequency Range

Radio Frequency RF 9 10 GHz

Local Oscillator LO 9 10 GHz

Intermediate Frequency IF 0.02 1 GHz

LO Input Level

−10

0

dBm

PERFORMANCE

Conversion Gain 10 13 dB

Gain Variation Range 10 15 dB

Noise Figure NF 2 2.5 dB

Image Rejection 15 20 dBc

Input Power for 1 dB Compression P1dB −4 dBm

Input Third-Order Intercept IP3 2 6 dBm

Input Second-Order Intercept IP2 12 dBm

Output Saturated Power

P

SAT

10

dBm

LO Leakage at the IF Port

1

−20 dBm

LO Leakage at the RF Port −37 −25 dBm

RF Leakage at the IF Port

1

−27 dBm

Amplitude Balance

1

3 dB

Phase Balance

1

4

Degree

Return Loss

RF Port 15 dB

LO Port 9 dB

IF Port

1

20 dB

POWER SUPPLY

LNA_VD1 20 mA

LNA_VD2 30 mA

BUFF_VD 40 mA

1

Measurements performed without external 90° hybrid at the IF ports.

HMC8108 Data Sheet

Rev. 0 | Page 4 of 18

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Drain Bias Voltage

LNA_VD1 5.8 V

LNA_VD2 4.8 V

BUFF_VD 4.2 V

Gate Bias Voltage

LNA_VG1 −2 V to + 0.15 V

LNA_VG2 −2 V to + 0.15 V

MIX_VG

−2 V to + 0.15 V

BUFF_VG −2 V to + 0.15 V

VCTRL −2 V to + 0.15 V

RF Input Power 20 dBm

LO Input Power 24 dBm

Maximum Peak Reflow Temperature (MSL3)

1

260°C

Maximum Junction Temperature 165°C

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to 150°C

Electrostatic Discharge (ESD) Sensitivity

Human Body Model (HBM) Class 0 (150 V)

Field Induced Charged Device Model (FICDM) Class C3 (250 V)

1

See the Ordering Guide section.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 3. Thermal Resistance

Package Type

θ

JA

θ

JC

Unit

E-32-1

1

93 119.47 °C/W

1

See JEDEC standard JESD51-2 for additional information on optimizing the

thermal impedance (PCB with 3 × 3 vias).

ESD CAUTION

Data Sheet HMC8108

Rev. 0 | Page 5 of 18

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

17

1

3

4

2

9

NIC

LNA_VG1

NIC

5

6

RFIN

NIC

7

VCTRL

8

NIC

18

NIC

19

NIC

20

LOIN

21

NIC

22

NIC

23

BUFF_VD

24

NIC

12

NIC

11

NIC

10

LNA_VG2

13

IF_I

14

NIC

15

MIX_VG

16

BUFF_VG

25

NIC

26

GND

27

NIC

28

IF_Q

29

NIC

30

LNA_VD2

31

NIC

32

LNA_VD1

HMC8108

TOP VIEW

(Not to Scale)

EPAD

15133-002

NOTES

1.

NIC = NOT INTERNALLY CONNECTED.

2. EXPOSED PAD. EXPOSED PAD MUST

BE CONNECTED TO RF/DC GROUND.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 4, 6, 8, 9, 11, 12,

14, 17 to 19, 21, 22,

24, 25, 27, 29, 31

NIC No Internal Connection. These pins are not connected internally.

3 LNA_VG1 Gate Bias Voltage for the First Low Noise Amplifier. See Figure 3 for the interface schematic.

5 RFIN Radio Frequency Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the interface

schematic.

7 VCTRL Voltage Control. Gate bias attenuation control for the low noise amplifier. See Figure 5 for the interface

schematic.

10 LNA_VG2 Gate Bias Voltage for the Second Low Noise Amplifier. See Figure 6 for the interface schematic.

13, 28 IF_I, IF_Q In-Phase and Quadrature Intermediate Frequency Output Pins. See Figure 7 for the interface schematic.

15 MIX_VG Gate Bias Voltage for FET Mixer. See Figure 8 for the interface schematic.

16 BUFF_VG Gate Bias Voltage for the Local Oscillator Buffer. See Figure 9 for the interface schematic.

20 LOIN Local Oscillator Input. This pin is ac-coupled and matched to 50 Ω. See Figure 10 for the interface schematic.

23

BUFF_VD

Drain Bias Voltage for the Local Oscillator Buffer. See Figure 11 for the interface schematic.

26 GND Ground Connect. This pin must be connected to RF/dc ground. See Figure 12 for the interface schematic.

30 LNA_VD2 Drain Bias Voltage for the Second Low Noise Amplifier. See Figure 13 for the interface schematic.

32 LNA_VD1 Drain Bias Voltage for the First Low Noise Amplifier. See Figure 14 for the interface schematic.

EPAD Exposed Pad. Connect the exposed pad to RF/dc ground. See Figure 12 for the interface schematic.

HMC8108LC5

HMC8108LC5

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