74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 4 November 2011 3 of 15
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of P
tot
derates linearly with 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input
1B, 2B, 3B, 4B 2, 5, 10, 13 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function selection
[1]
Input Output
nA nB nY
LLZ
LHZ
HLZ
HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
< 0 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
< 0 50 - mA
V
O
output voltage active mode
[2]
0.5 +6.5 V
high-impedance mode
[2]
0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CC
-50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
-500 mW
