74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 4 November 2011 7 of 15
NXP Semiconductors
74LVC38A
Quad 2-input NAND gate; open-drain
Test data is given in Table 9.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
C
L
R
T
R
L
R
L
G
Table 9. Test data
Supply voltage Input Load V
EXT
V
I
t
r
, t
f
C
L
R
L
t
PLH
, t
PHL
t
PLZ
, t
PZL
1.2 V V
CC
2 ns 30 pF 1 k open 2 V
CC
1.65 V to 1.95 V V
CC
2 ns 30 pF 1 k open 2 V
CC
2.3 V to 2.7 V V
CC
2 ns 30 pF 500 open 2 V
CC
2.7V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 V
CC
