ZL30723 Product Brief
3
Microsemi Corporation
Truly hitless reference switching with <200ps output clock phase transient
o Physical-clock-to-physical-clock reference switching
o Physical-clock-to-packet-timing reference switching
o Packet-timing-to-physical-clock reference switching
o Packet-timing-to-packet-timing reference switching
Support for SyncE and SONET/SDH equipment clock specifications
o ITU-T G.8262 option 1 EEC
o ITU-T G.8262 option 2 EEC
o ITU-T G.813 option 1 SEC
o IUT-T G.813 option 2 SEC
Output phase adjustment in 10ps steps
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
Holdover frequency averaging with programmable averaging time and delay time
2.4 APLL Features
APLL with very high-resolution fractional scaling (i.e. non-integer) per channel
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Bypass mode supports system testing
2.5 Output Clock Features
Three low-jitter output clocks per channel
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
Output jitter as low as 0.25ps RMS (12kHz to 20MHz)
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(Example 1: OC3P 125MHz, OC3N 25MHz. Example 2: OC2P 25MHz, OC2N 1Hz)
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Sophisticated output-to-output phase alignment
Per-output phase adjustment with high resolution and unlimited range
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
2.6 General Features
SPI or I
2
C serial microprocessor interface per channel
Automatic self-configuration at power-up from internal EEPROM memory; pin control to specify one of
four stored configurations
Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency with
resolution better than 0.01ppb
Input-to-output alignment with external feedback
Four general-purpose I/O pins per channel each with many possible status and control options
Output frame sync signals: 2kHz or 8kHz (SONET/SDH), 1Hz (IEEE 1588) or other frequency
Internal compensation for local oscillator frequency error
2.7 API Software
Interfaces to 1588-capable PHYs and switches with integrated timestamping
Abstraction layer for independence from OS and CPU, from embedded SoC to home-grown
Fits into centralized, highly integrated “pizza box” architectures as well as distributed architectures with
multiple line cards and timing cards
