AT49LV002-90VI Datasheet AT49LV002-90PC, AT49LV002-90TI, AT49LV002NT-90JC | P4-P6

AT49BV/LV002(N)(T)

0982D–FLASH–02/03

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a

logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to

a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle operation (please refer to the Command

Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE

or CE, whichever occurs

last, and the data latched on the rising edge of WE

or CE, whichever occurs first. Program-

ming is completed after the specified t

cycle time. The DATA polling feature may also be

used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has

a programming lockout feature. This feature prevents programming of data in the designated

block once the feature has been enabled. The size of the block is 16K bytes. This block,

referred to as the boot block, can contain secure code that is used to bring up the system.

Enabling the lockout feature will allow the boot code to stay in the device while data in the rest

of the device is updated. This feature does not have to be activated; the boot block’s usage as

a write protected region is optional to the user. The address range of the boot block is 00000

to 03FFF for the AT49BV/LV002(N) while the address range of the boot block is 3C000 to

3FFFF for the AT49BV/LV002(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed with input voltage of 5.5V or less. Data in the main memory block can still be

changed through the regular programming method. To activate the lockout feature, a series of

six program commands to specific addresses with specific data must be performed. Please

refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if pro-

gramming of the boot block section is locked out. When the device is in the software product

identification mode (see Software Product Identification Entry and Exit sections) a read from

address location 00002H will show if programming the boot block is locked out for the

AT49BV/LV002(N), and a read from address location 3C002H will show if programming the

bootblock is locked out for AT49BV/LV002(N)T. If the data on I/O0 is low, the boot block can

be programmed; if the data on I/O0 is high, the program lockout feature has been activated

and the block cannot be programmed. The software product identification code should be

used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot

block programming lockout by taking the RESET

pin to 12 volts during the entire chip erase,

sector erase or byte programming operation. When the RESET

pin is brought back to TTL lev-

els the boot block programming lockout feature is again active. This feature is not available on

the AT49BV/LV002N(T).

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification.

The manufacturer and device code is the same for both modes.

AT49BV/LV002(N)(T)

0982D–FLASH–02/03

DATA POLLING: The AT49BV/LV002(N)(T) features DATA polling to indicate the end of a

program cycle. During a program cycle an attempted read of the last byte loaded will result in

the complement of the loaded data on I/O7. Once the program cycle has been completed, true

data is valid on all outputs and the next cycle may begin. DATA

polling may begin at any time

during the program cycle.

TOGGLE BIT: In addition to DATA

polling the AT49BV/LV002(N)(T) provides another method

for determining the end of a program or erase cycle. During a program or erase operation,

successive attempts to read data from the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be

read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs

to the AT49BV/LV002(N)(T) in the following ways: (a) V

sense: if V

is below 1.8V (typical),

the program function is inhibited. (b) Program inhibit: holding any one of OE

low, CE high or

high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

AT49BV/LV002(N)(T)

0982D–FLASH–02/03

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)

2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV002(N) and 3C000H to 3FFFFH for

the AT49BV/LV002(N)T

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses:

For the AT49BV/LV002(N):

SA = 00000 to 03FFF for BOOT BLOCK

Nothing will happen and the device goes back to the read mode in 100 ns

SA = 04000 to 05FFF for PARAMETER BLOCK 1

SA = 06000 to 07FFF for PARAMETER BLOCK 2

SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1

This command will erase - PB1, PB2 and MMB1

SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2

For the AT49BV/LV002(N)T:

SA = 3C000 to 3FFFF for BOOT BLOCK

Nothing will happen and the device goes back to the read mode in 100 ns

SA = 3A000 to 3BFFF for PARAMETER BLOCK 1

SA = 38000 to 39FFF for PARAMETER BLOCK 2

SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1

This command will erase - PB1, PB2 and MMB1

SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2

Command Definition (in Hex)

(1)

Command

Sequence

Bus

Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 Addr D

OUT

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(4)

Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Boot Block Lockout

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID Entry 3 5555 AA 2AAA 55 5555 90

Product ID Exit

(3)

3 5555 AA 2AAA 55 5555 F0

Product ID Exit

(3)

1 XXXX F0

Absolute Maximum Ratings

Temperature Under Bias................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions beyond those indicated in the operational sec-

tions of this specification is not implied. Exposure to

absolute maximum rating conditions for extended

periods may affect device reliability.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

AT49LV002-90VI

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AT49LV002-90VI

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