LTC3255
10
3255f
For more information www.linear.com/LTC3255
APPLICATIONS INFORMATION
Power Good Output Operation (PGOOD)
The LTC3255 includes an open-drain power good (PGOOD)
output pin. If the chip is in shutdown or undervoltage
lockout, or if the FB pin voltage is less than 90% (typi-
cal) of its regulation voltage, PGOOD is low impedance
to ground. PGOOD becomes high impedance when V
OUT
rises to 94% (typical) of its regulation voltage. PGOOD
stays high impedance until V
OUT
is shut down or drops
below the PGOOD falling threshold (90% typical). A pull-
up resistor can be inserted between PGOOD and V
OUT
to
signal a valid power good condition. The use of a large
value pull-up resistor on PGOOD and a capacitor placed
between PGOOD and GND can be used to delay the PGOOD
signal if desired.
V
IN
Shunt Regulator Operation
The V
IN
shunt regulator feature of the LTC3255 is intended
for applications where V
IN
is current-fed, such as in 4mA
to 20mA current loops. A circuit powered by a current
loop must limit the voltage drop it presents to the loop to
avoid exceeding the loop compliance, which would break
the current loop. The LTC3255’s V
IN
shunt regulator moni-
tors V
IN
and V
OUT
, drawing V
IN
current as necessary to
keep V
IN
from rising much beyond 3V above twice V
OUT
.
The shunt regulator is enabled by connecting the SHUNT
pin to the BIAS pin in the circuit board layout. The shunt
is disabled by connecting the SHUNT pin to GND.
The shunt regulator dissipates power which must be ac-
counted for in thermal budgeting. Total power dissipation
(P
DSHUNT
) in the LTC3255 with shunt regulator enabled is
equal to the input power minus the output power of the
LTC3255, or approximately:
P
D(SHUNT)
= P
IN
P
OUT
= V
IN
I
IN
V
OUT
I
OUT
2 V
OUT
+ 2V
( )
I
IN
V
OUT
I
OUT
where I
IN
is the time-averaged current being fed into V
IN
by the current loop, V
OUT
is the output voltage, and I
OUT
is the output load current. Notice that the largest power
dissipation occurs when output load current is zero. This
is because any power fed into V
IN
must be dissipated in
either the load or the LTC3255. If the load is not drawing
any current, then the LTC3255 must dissipate all of the
input power.
When the shunt regulator is enabled, the LTC3255 charge
pump is locked in 2:1 mode. To achieve output regulation,
the input current to the part must have sufficient voltage
compliance above twice V
OUT
. The graph in Figure 2 shows
the typical minimum compliance required at the V
IN
pin
for correct operation. For V
OUT
≤ 5.5V, a V
IN
compliance
of 2V
OUT
+ 3.5V is recommended. For V
OUT
> 5.5V, a V
IN
compliance of 2V
OUT
+ 4V is recommended.
TEMPERATURE (°C)
60
2.5
V
IN
– 2 • V
OUT
(V)
2.6
2.8
2.9
3.0
3.5
3.2
0
60
90 120
3255 F02
2.7
3.3
3.4
3.1
30
30
150
I
VIN
= 20mA
V
OUT
= 2.5V
V
OUT
= 3.3V
V
OUT
= 5V
V
OUT
= 12V
Figure 2. Typical Minimum V
IN
– 2 • V
OUT
Compliance Required
for Shunt Mode Operation
LTC3255
11
3255f
For more information www.linear.com/LTC3255
APPLICATIONS INFORMATION
V
OUT
Ripple and Capacitor Selection
The type and value of capacitors used with the LTC3255
determine several important parameters such as output
ripple and charge pump strength. The value of C
OUT
directly controls the amount of output ripple for a given
load current. Increasing the size of C
OUT
will reduce the
output ripple.
To reduce output noise and ripple, it is suggested that a
low ESR (equivalent series resistance < 0.1Ω) ceramic
capacitor (10μF or greater) be used for C
OUT
. Ceramic
capacitors typically have exceptionally low ESR which,
combined with a tight board layout, should yield excellent
performance. Tantalum and aluminum capacitors can be
used in parallel with a ceramic capacitor to increase the
total capacitance but are not recommended to be used
alone because of their high ESR.
V
IN
Capacitor Selection
The
total amount and type of capacitance necessary for
input bypassing is very dependent on the impedance of
the input power source as well as existing bypassing al-
ready on the V
IN
node. For optimal input noise and ripple
reduction, it is recommended that a low ESR ceramic
capacitor be used for C
IN
bypassing. Low ESR will reduce
the voltage steps caused by changing input current, while
the absolute capacitor value will determine the level of
ripple. An electrolytic or tantalum capacitor may be used
in parallel with the ceramic capacitor on C
IN
to increase
the total capacitance, but due to the higher ESR, it is not
recommended that an electrolytic or tantalum capacitor be
used alone for input bypassing. The LTC3255 will operate
with capacitors less thanF, but depending on the
source
impedance, input noise can feed through to the output
causing degraded performance. For best performance,
1μF or greater total capacitance is suggested for C
IN
.
Flying Capacitor Selection
The flying capacitor should always be a ceramic type.
Polarized capacitors such as tantalum or aluminum electro-
lytics are not recommended. The flying capacitor controls
the strength of the charge pump. In order to achieve the
rated output
current, it is necessary for the flying capaci-
tor to have at least 0.4μF of capacitance over operating
temperature with a bias voltage equal to the programmed
V
OUT
(see Ceramic Capacitor Selection Guidelines). The
voltage rating of the ceramic capacitor should be V
OUT
+
1V or greater.
Ceramic Capacitor Selection Guidelines
Capacitors of different materials lose their capacitance
with higher temperature and voltage at different rates.
For
example, a ceramic capacitor made of X5R or X7R
material will retain most of its capacitance from –40°C
to 85°C, whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range (60% to 80%
loss typical). Z5U and Y5V capacitors may also have a
very strong voltage coefficient, causing them to lose an
additional 60% or more of their capacitance when
the rated
voltage is applied. Therefore, when comparing different
capacitors, it is often more appropriate to compare the
amount of achievable capacitance for a given case size
rather than discussing the specified capacitance value. For
example, over rated voltage and temperature conditions,
a 4.7μF, 10V, Y5V ceramic capacitor in an 0805 case may
not provide any more capacitance than aF, 10V, X5R
or X7R
available in the same 0805 case. In fact, over bias
and temperature range, theF, 10V, X5R or X7R will
provide more capacitance than the 4.7μF, 10V, Y5V. The
capacitor manufacturer’s data sheet should be consulted
to determine what value of capacitor is needed to ensure
minimum capacitance values are met over operating
temperature and bias voltage. Table 1 is a list of ceramic
capacitor
manufacturers in alphabetical order:
LTC3255
12
3255f
For more information www.linear.com/LTC3255
APPLICATIONS INFORMATION
Table 1
CERAMIC CAPACITOR MANUFACTURER WEBSITE
AVX www.avxcorp.com
Kemet www.kemet.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
TDK www.tdk.com
Layout Considerations
Due to the high switching frequency and transient cur-
rents produced by the LTC3255, careful board layout is
necessary for optimal performance. A true ground plane
and short connections to all capacitors will optimize
performance, reduce noise and ensure proper regulation
over all conditions.
When using the LTC3255 with an external resistor divider
it is important to minimize any stray capacitance to the FB
node. Stray capacitance from FB to C
+
or C
can degrade
performance significantly and should be minimized and/
or shielded if necessary.
Thermal Management
The on chip power dissipation in the LTC3255 will cause
the junction to ambient temperature to rise at a rate of
40°
C/W or more in the MSE package, or 43°C/W or more
in the DD package. To reduce the maximum junction
temperature, a good thermal connection to the PC board
is recommended. Connecting the die paddle (Pin 11) to a
large ground plane under the device can reduce the thermal
resistance of the package and PC board considerably. Poor
board layout and failure to connect the die
paddle (Pin
11) to a large ground plane can result in thermal junction
to ambient impedance well in excess of 40°C/W (MSE
package) or in excess of 43°C/W (DD package). Thermal
junction to ambient impedance is specified per JEDEC
standard JESD 51-5.
Because of the wide input operating range it is possible to
exceed the specified operating junction temperature and
even reach thermal shutdown. It is the
responsibility of
the user of the LTC3255 to calculate worst-case operat-
ing conditions (temperature and power) to make sure
the LTC3255’s specified operating junction temperature
is not exceeded for extended periods of time. The 2:1
Step-Down, 1:1 Step-Down, and V
IN
Shunt Regulator
Operation sections provide equations for calculating the
power dissipation (P
D
) in each mode.
For example, if it is determined that the
maximum power
dissipation (P
D
) is 1.2W under normal operation, then
the maximum junction to ambient temperature rise in the
MSE package will be:
Junction to Ambient = 1.2W • 40°C/W = 48°C
Thus, the ambient temperature under this condition can
not exceed 102°C if the junction temperature is to remain
below 150°C. For ambient temperatures exceeding roughly
127°C, the device will cycle in and out of the thermal
shutdown.

LTC3255EMSE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers Wide VIN Range Fault Protected 50mA Step-Down Charge Pump
Lifecycle:
New from this manufacturer.
Delivery:
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