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95V850AGLFT

P1-P3P4-P6P7-P9P10-P10
4
ICS95V850
0458G—11/21/08
Timing Requirements
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating clock frequency freq
op
66 210 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
Recommended Operating Condition
(see note1)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DD
, A
VDD
2.3 2.5 2.7 V
CLK_INT, CLK_INC, FB_INC 0.4 V
DD
/2 - 0.18 V
CLK_INT, CLK_INC (Universal Input) -0.3 V
DD
- 0.4 V
CLK_INT, CLK_INC, FB_INC V
DD
/2 + 0.18 2.1 V
CLK_INT, CLK_INC (Universal Input) 0.4 V
DD
+ 0.3 V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DD
+ 0.3 V
DC - CLK_INT, FB_INT 0.36 V
DD
+ 0.6 V
AC - CLK_INT, FB_INT (Universal Input) 0.4 V
DD
+ 0.6 V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
(Universal Input) 0.45(V
IH
- V
IL
) 0.55(V
IH
- V
IL
)V
High level output
current
I
OH
-6.4 mA
Low level output current I
OL
5.5 mA
Operating free-air
temperature
T
A
085°C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage V
IL
High level input voltage V
IH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal must be crossing.
5
ICS95V850
0458G—11/21/08
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output 5.5 ns
High-to low level propagation
delay time
t
PLL
1
CLK_IN to any output 5.5 ns
Period jitter T
jit (per)
100MHz to 200MHz -30 30 ps
Half-period jitter t(jit_hper) 100MHz to 200MHz -75 30 ps
Input clock slew rate t
sl(i)
14V/ns
Output clock slew rate t
sl(o)
12.5V/ns
Cycle to Cycle Jitter
1
T
cyc
-T
cyc
100MHz to 200MHz 60 ps
Phase error
t
(phase error)
4
-50 0 50 ps
Output to Output Skew T
skew
60 ps
6
ICS95V850
0458G—11/21/08
GND
ICS95V850
V
DD
V
DD
/2
V
(CLKC)
V
(CLKC)
SCOPE
C=14pF
-V
DD/2
-V
DD/2
-V
DD/2
V
DD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V
(TT)
V
(TT)
C=14pF
NOTE: V
(TT)
=
GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS95V850
Figure 3. Cycle-to-Cycle Jitter
P1-P3P4-P6P7-P9P10-P10

95V850AGLFT

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IC CLK BUF DDR 210MHZ 1CIRC
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