AT29C512-70JU Datasheet AT29C512-90JU, AT29C512-70JU, AT29C512-70TU | P1-P3

Features

• Fast Read Access Time – 70 ns

• 5-volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)

– 512 Sectors (128 Bytes/Sector)

– Internal Address and Data Latches for 128 Bytes

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Fast Sector Program Cycle Time – 10 ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 50 mA Active Current

– 300 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• Green (Pb/Halide-free) Packaging Option

1. Description

The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only

memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man-

ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers

access times to 70 ns with power dissipation of just 275 mW over the industrial tem-

perature range. When the device is deselected, the CMOS standby current is less

than 300 µA. The device endurance is such that any sector can typically be written to

in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C512 does not require high

input voltages for programming. Five-volt-only commands determine the operation of

the device. Reading data out of the device is similar to reading from an EPROM.

Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are

loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation

of a program cycle, the device will automatically erase the sector and then program

the latched data using an internal control timer. The end of a program cycle can be

detected by DATA

polling of I/O7. Once the end of a program cycle has been

detected, a new access for a read or program can begin.

512K (64K x 8)

5-volt Only

Flash Memory

AT29C512

0456i–FLASH–9/08

AT29C512

2. Pin Configurations

2.1 32-lead PLCC Top View

2.2 32-lead TSOP (Type 1) Top View

Pin Name Function

A0 - A15 Addresses

CE Chip Enable

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

VCC

A11

A13

A14

VCC

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

0456i–FLASH–9/08

AT29C512

3. Block Diagram

4. Device Operation

4.1 Read

The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data

stored at the memory location determined by the address pins is asserted on the outputs. The

outputs are put in the high impedance state whenever CE

or OE is high. This dual-line control

gives designers flexibility in preventing bus contention.

4.2 Byte Load

Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes

for data protection. A byte load is performed by applying a low pulse on the WE

or CE input with

or WE low (respectively) and OE high. The address is latched on the falling edge of CE or

, whichever occurs last. The data is latched by the first rising edge of CE or WE.

4.3 Program

The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,

data for the entire sector must be loaded into the device. Any byte that is not loaded during the

programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the

device, they are simultaneously programmed during the internal programming period. After the

first data byte has been loaded into the device, successive bytes are entered in the same man-

ner. Each new byte to be programmed must have its high-to-low transition on WE

(or CE) within

150 µs of the low-to-high transition of WE

(or CE) of the preceding byte. If a high-to-low transi-

tion is not detected within 150 µs of the last low-to-high transition, the load period will end and

the internal programming period will start. A7 to A15 specify the sector address. The sector

address must be valid during each high-to-low transition of WE

(or CE). A0 to A6 specify the

byte address within the sector. The bytes may be loaded in any order; sequential loading is not

required. Once a programming operation has been initiated, and for the duration of t

, a read

operation will effectively be a polling operation.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

AT29C512-70JU

Mfr. #:

Buy AT29C512-70JU

Manufacturer:

Microchip Technology / Atmel

Description:

NOR Flash 64K x 8 70 ns 4.5V-5.5V

Lifecycle:

New from this manufacturer.

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AT29C512-70JU

AT29C512-70JU

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