3. Block Diagram
Figure 3-1. ATtiny212 / ATtiny412 Block Diagram
I
N
/
O
U
T
D
A
T
A
B
U
S
Clock generation
BUS Matrix
CPU
USART0
SPI0
CCL
AC0
ADC0
TCA0
TCB0
AINP0
AINN0
OUT
AIN
[6, 7, 3:0]
WO[5:0]
RXD
TXD
XCK
XDIR
MISO
MOSI
SCK
SS
PORTS
System
Management
SLPCTRL
RSTCTRL
CLKCTRL
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
UPDI
CRC
SRAM
NVMCTRL
Flash
EEPROM
OSC20M
OSC32K
Detectors/
references
BOD/
VLM
POR
Bandgap
WDT
RTC
CPUINT
M M
S
M
S
S
OCD
RST
S
EXTCLK
LUTn-IN[2:0]
LUTn-OUT
WO
CLKOUT
PA[7:0]
GPIOR
TWI0
SDA
SCL
TCD0
WO[A,B,C,D]
XOSC32k
TOSC2
TOSC1
To
detectors
UPDI / RESET
EVSYS
EVOUT[n:0]
DAC0
OUT
ATtiny212/412
© 2017 Microchip Technology Inc.
Datasheet Preliminary Summary
DS40001931A-page 7
4. Pinout
4.1 8-pin SOIC
VDD
GND
PA2
PA6
PA7
PA1
1
2
3
4
5
6
7
8
GPIO VDD power domain
Clock, crystal
Programming, Debug, ResetInput supply
Ground
Analog function
Digital function only
PA3/EXTCLK
PA0/RESET/UPDI
ATtiny212/412
© 2017 Microchip Technology Inc.
Datasheet Preliminary Summary
DS40001931A-page 8
5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Table 5-1. PORT Function Multiplexing
SOIC 8-pin
Pin Name
(1,2)
Other/
Special
ADC0 AC0 DAC0 USART0 SPI0 TWI0 TCA0 TCB0 TCD0 CCL
6 PA0
RESET
UPDI
AIN0 LUT0-IN0
4 PA1 BREAK AIN1
TXD
MOSI
SDA
LUT0-IN1
5 PA2 EVOUT0 AIN2
RxD
MISO
SCL
LUT0-IN2
7 PA3 EXTCLK AIN3
XCK
SCK WO3
8 GND
1 VDD
2 PA6 AIN6 AINN0 OUT
3 PA7 AIN7 AINP0 LUT1-OUT
Note: 
1. Pins names are of type Pxn, with x being the PORT instance (A,B) and n the pin number. Notation
for signals is PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full
asynchronous detection.
Tip:  Signals on alternative pin locations are in typewriter font.
ATtiny212/412
© 2017 Microchip Technology Inc.
Datasheet Preliminary Summary
DS40001931A-page 9

ATTINY412-SSNR

Mfr. #:
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU 105C, Green, 20MHz, SOIC8, T&R
Lifecycle:
New from this manufacturer.
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