ST16C450
10
Rev. 4.20
Figure 3, EXTERNAL CRYSTAL OSCILLATOR
CONNECTION
Loopback Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. In this mode MSR bits 4-7 are
also disconnected. However, MCR register bits 0-3
can be used for controlling loop-back diagnostic test-
ing. In the loop-back mode -OP1 and -OP2 in the MCR
register (bits 0-1) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 4). The -CTS, -DSR, -CD,
and -RI are disconnected from their normal modem
control inputs pins, and instead are connected inter-
nally to -DTR, -RTS, -OP1 and -OP2. Loop-back test
data is entered into the transmit holding register via the
user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the
receive UART via the internal loop-back connection. The
receive UART converts the serial data back into parallel
data that is then made available at the user data
interface, D0-D7. The user optionally compares the
received data to the initial transmitted data for verifying
error free operation of the UART TX/RX circuits.
In this mode , the receiver and transmitter interrupts are
fully operational. The Modem Control Interrupts are also
operational. However, the interrupts can only be read
using lower four bits of the Modem Control Register
(MCR bits 0-3) instead of the four Modem Status
Register bits 4-7. The interrupts are still controlled by
the IER.
C1
22pF
C2
33pF
X1
1.8432 MHz
R1
50-120
R2
1M
XTAL1
XTAL2
ST16C450
11
Rev. 4.20
Figure 4, INTERNAL LOOPBACK MODE DIAGRAM
D0-D7
-IOR,IOR
-IOW,IOW
RESET
A0-A2
-AS
CS0,CS1
-CS2
INT
TX
RX
Data bus
&
Control Logic
Register
Select
Logic
Modem Control Logic
Interrupt
Control
Logic
Transmit
Holding
Registers
Transmit
Shift
Register
Receive
Holding
Registers
Receive
Shift
Register
Inter Connect Bus Lines
&
Control signals
Clock
&
Baud Rate
Generator
XTAL1
RCLK
XTAL2
-BAUDOUT
-CTS
-RTS
-DTR
-DSR
-RI
-CD
-OP1
-OP2
MCR Bit-4=1
-DDIS
CSOUT
ST16C450
12
Rev. 4.20
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C450 internal registers. The as-
signed bit functions are more fully defined in the following paragraphs.
Table 4, ST16C450 INTERNAL REGISTERS
A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
[Default]
Note *5
General Register Set
0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 IER [00] 0000modem receive transmit receive
status line holding holding
interrupt status register register
interrupt
0 1 0 ISR [01] 0000INTINTINTINT
priority priority priority status
bit-2 bit-1 bit-0
0 1 1 LCR [00] divisor set set even parity stop word word
latch break parity parity enable bits length length
enable bit-1 bit-0
1 0 0 MCR [00] 0 0 0 loop -OP2 -OP1 -RTS -DTR
back
1 0 1 LSR [60] 0 trans. trans. break framing parity overrun receive
empty holding interrupt error error error data
empty ready
1 1 0 MSR [X0] CD RI DSR CTS delta delta delta delta
-CD -RI -DSR -CTS
1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Special Register Set: Note *3
0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
Note *3: The Special register set is accessible only when LCR bit-7 is set to a logic 1.
Note *5: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.

ST16C450CQ48-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
UART Interface IC SINGLE UART
Lifecycle:
New from this manufacturer.
Delivery:
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