CY7C1046DV33
4-Mbit (1 M × 4) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05611 Rev. *F Revised November 19, 2014
4-Mbit (1 M × 4 ) Static RAM
Features
■ Pin- and function-compatible with CY7C1046CV33
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 90 mA @ 100 MHz
■ Low CMOS standby power
❐ I
SB2
= 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in lead-free 400-mil-wide 32-pin SOJ package
Functional Description
The CY7C1046DV33 is a high-performance CMOS static RAM
organized as 1M words by 4 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE
), and tri-state drivers. Writing to the device is
accomplished by taking Chip Enable (CE
) and Write Enable
(WE
) inputs LOW. Data on the four I/O pins (I/O
0
through I/O
3
)
is then written into the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing Write Enable
(WE
) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), or during a Write operation
(CE
LOW, and WE LOW).
The CY7C1046DV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground
(revolutionary) pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
1 Mbit x 4
I/O
3
I/O
2
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
A
9
A
18
A
10
A
19
