CAT5172
http://onsemi.com
4
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions (continued)
V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; –40C < T
A
< +85C; unless otherwise noted.
Parameter UnitMax
Typ
(Note 3)
MinSymbolTest Conditions
DYNAMIC CHARACTERISTICS (Notes 8 and 10)
Bandwidth –3 dB
R
AB
= 50 kW / 100 kW, Code = 0x80
BW 100/40 kHz
Total Harmonic Distortion V
A
=1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 kW
THD
W
0.05 %
V
W
Settling Time (50 kW/100 kW)
V
A
= 5 V, V
B
= 0 V, 1 LSB error band t
S
2
ms
3. Typical specifications represent average readings at +25C and V
DD
= 5 V.
4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are
guaranteed monotonic.
5. V
AB
= V
DD
, Wiper (V
W
) = no connect.
6. INL and DNL are measured at VW with the digital POT configured as a potentiometer divider similar to a voltage output D/A converter.
V
A
= V
DD
and V
B
= 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8. Guaranteed by design and not subject to production test.
9. PDISS is calculated from (I
DD
x V
DD
). CMOS logic level inputs result in minimum power dissipation.
10.All dynamic characteristics use V
DD
= 5 V.
Table 5. TIMING CHARACTERISTICS: 50 kW and 100 kW Versions
V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; –40C < T
A
< +85C; unless otherwise noted.
Parameter
Test Conditions Symbol Min
Typ
(Note 11)
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS (Notes 12 and 13) (Specifications Apply to All Parts)
Clock Frequency
f
CLK
25 MHz
Input Clock Pulse width Clock level high or low t
CH
, t
CL
20 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CS Setup Time T
CSS
15 ns
CS High Pulse Width T
CSW
40 ns
CLK Fall to CS Fall Hold Time T
CSH0
0 ns
CLK Fall to CS Rise Hold Time T
CSH1
0 ns
CS Rise to Clock Rise Setup T
CS1
10 ns
11. Typical specifications represent average readings at +25C and V
DD
= 5 V.
12.Guaranteed by design and not subject to production test.
13. See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V.
