WLED/RGB Backlight Driver for Medium Size LCDs
A8504
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PCB Layout Guidelines
The A8504 evaluation board provides a useful model for design-
ing application circuit layouts. The following guidelines should
be observed:
• Place the supply bypass capacitor, C8, close to the VIN pin and
the ground plane.
• Route analog ground, digital signal ground, LED ground
(LGND pin), and power ground (PGND pin) separately. Con-
nect all these grounds at the pad for the exposed thermal pad
under the A8504, serving as a star ground.
• Place the input capacitors, C2 and C7, the inductor, L1, the
boost diode D1, and the internal MOSFET and output capaci-
tor, C4, so that they form the smallest loop practical. Avoid
long traces for these paths.
• Place the RISET, RFSET, and OVP resistors and the compensa-
tion capacitor, C5, close to the ISET, FSET, OVP, and COMP
pins, respectively.
• Provide a substantial solder pad under the exposed thermal
pad on the bottom side of the A8504, to provide good thermal
conduction. Connect the PCB solder pad to the PCB ground
plane with multiple thermal vias. For a thermal via specifica-
tion, please refer to JEDEC guidelines.
• For best thermal performance, avoid thermal stresses.
V
OUT
V
BAT
V
IN
L1
COUT
CBAT
D1
ROVP
RPWM
GND
RISET
RFSET
CC
CIN
A8504
PAD
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
26
25
24
23
22
AGND
VIN
SW
SW
OVP
LED3
LED5
LED7
LGND
LED8
LED6
LED4
PGND
PWM
GND
SEL3
SEL2
SEL1
LED2
PGND
SKIP
COMP
FSET
ISET
GND
LED1
Figure 13. Schematic diagram of A8504 typical application circuit and composite view of typical PCB
layout. In the composite view, the red line superimposed represents the current loop during switch
on-time (return through the A8504 device and the PCB ground plane). The green line represents the
current loop during off-time. Both of these loops should be designed to be as short as practicable.
