AD7949SCPZ-EP-R2

AD7949-EP Enhanced Product
Rev. A | Page 4 of 12
Parameter Test Conditions/Comments Min Typ Max Unit
INTERNAL REFERENCE
REF Output Voltage 2.5 V, @ 25°C 2.490 2.500 2.510 V
4.096 V, @ 25°C 4.086 4.096 4.106 V
REFIN Output Voltage
7
2.5 V, @ 25°C 1.2 V
4.096 V, @ 25°C 2.3 V
REF Output Current ±300 µA
Temperature Drift ±10 ppm/°C
Line Regulation VDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time CREF = 10 µF 5 ms
EXTERNAL REFERENCE
Voltage Range REF input 0.5 VDD + 0.3 V
REFIN input (buffered) 0.5 VDD − 0.5 V
Current Drain 250 kSPS, REF = 5 V 50 µA
TEMPERATURE SENSOR
Output Voltage
8
@ 25°C 283 mV
Temperature Sensitivity 1 mV/°C
DIGITAL INPUTS
Logic Levels
V
IL
−0.3 +0.3 × VIO V
V
IH
0.7 × VIO VIO + 0.3 V
I
IL
−1 +1 µA
I
IH
−1 +1 µA
DIGITAL OUTPUTS
Data Format
9
Pipeline Delay
10
V
OL
I
SINK
= +500 µA 0.4 V
V
OH
I
SOURCE
= −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
Operating range 1.8 VDD + 0.3 V
Standby Current
11,
12
VDD and VIO = 5 V, @ 25°C 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.5 µW
VDD = 2.5 V, 100 kSPS throughput 1.45 2.0 mW
VDD = 2.5 V, 200 kSPS throughput 2.9 4.0 mW
VDD = 5 V, 250 kSPS throughput 10.8 12.5 mW
VDD = 5 V, 250 kSPS throughput with internal
reference
13.5 15.5 mW
Energy per Conversion 50 nJ
TEMPERATURE RANGE
13
Specified Performance T
MIN
to T
MAX
−55 +125 °C
1
See the AD7949 data sheet.
2
The bandwidth is set in the configuration register.
3
LSB means least significant bit. With the 5 V input range, one LSB = 305 µV.
4
See the AD7949 data sheet. These specifications include full temperature range variation but not the error contribution from the external reference.
5
With VDD = 5 V, unless otherwise noted.
6
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
7
This is the output from the internal band gap.
8
The output voltage is internal and present on a dedicated multiplexer input.
9
Unipolar mode: serial 14-bit straight binary.
Bipolar mode: serial 14-bit twos complement.
10
Conversion results available immediately after completed conversion.
11
With all digital inputs forced to VIO or GND as required.
12
During acquisition phase.
13
Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Enhanced Product AD7949-EP
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications 55 °C to +125 °C, unless otherwise noted.
Table 3.
Parameter
1
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
2.2 µs
Acquisition Time t
ACQ
1.8 µs
Time Between Conversions t
CYC
4.0 µs
Data Write/Read During Conversion t
DATA
1.0 µs
CNV Pulse Width t
CNVH
10 ns
SCK Period t
SCK
t
DSDO
+ 2 ns
SCK Low Time t
SCKL
11 ns
SCK High Time t
SCKH
11 ns
SCK Falling Edge to Data Remains Valid t
HSDO
4 ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 23 ns
VIO Above 1.8 V 28 ns
CNV Low to SDO D15 MSB Valid t
EN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V
22
ns
VIO Above 1.8 V 25 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
DIS
32 ns
CNV Low to SCK Rising Edge t
CLSCK
10 ns
DIN Valid Setup Time from SCK Rising Edge t
SDIN
5 ns
DIN Valid Hold Time from SCK Rising Edge t
HDIN
5 ns
1
See Figure 2 and Figure 3 for load conditions.
Rev. A | Page 5 of 12
AD7949-EP Enhanced Product
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications 55 °C to +125 °C, unless otherwise noted.
Table 4.
Parameter
1
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
CONV
3.2 µs
Acquisition Time t
ACQ
1.8 µs
Time Between Conversions t
CYC
5 µs
Data Write/Read During Conversion
t
DATA
1.2
µs
CNV Pulse Width t
CNVH
10 ns
SCK Period t
SCK
t
DSDO
+ 2 ns
SCK Low Time t
SCKL
12 ns
SCK High Time t
SCKH
12 ns
SCK Falling Edge to Data Remains Valid
t
HSDO
5
ns
SCK Falling Edge to Data Valid Delay t
DSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 38 ns
VIO Above 1.8 V 48 ns
CNV Low to SDO D15 MSB Valid t
EN
VIO Above 3 V 21 ns
VIO Above 2.7 V 27 ns
VIO Above 2.3 V 35 ns
VIO Above 1.8 V 45 ns
CNV High or Last SCK Falling Edge to SDO High Impedance t
DIS
50 ns
CNV Low to SCK Rising Edge t
CLSCK
10 ns
DIN Valid Setup Time from SCK Rising Edge t
SDIN
5 ns
DIN Valid Hold Time from SCK Rising Edge t
HDIN
5 ns
1
See Figure 2 and Figure 3 for load conditions.
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
09822-003
Figure 3. Voltage Levels for Timing
Rev. A | Page 6 of 12

AD7949SCPZ-EP-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8 ch 250ksps 14bit ADC IC
Lifecycle:
New from this manufacturer.
Delivery:
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