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IDT79RC32V333-100DHG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
16 of 30 May 4, 2004
IDT 79RC32333
pci_idsel, pci_req_n[2],
pci_req_n[1], pci_req_n[0],
pci_gnt_n[0], pci_inta_n
Thld pci_clk rising 0—0—0—ns
pci_eeprom_mdi Tsu pci_clk rising,
pci_eeprom_sk falling
15 — 12 — 10 — ns
pci_eeprom_mdi Thld pci_clk rising,
pci_eeprom_sk falling
15 — 12 — 10 — ns
pci_eeprom_mdo, pci-eeprom_cs Tdo pci_clk rising,
pci_eeprom_sk falling
—15—12—10 ns
pci_eeprom_sk Tdo pci_clk rising — 15 — 12 — 10 ns
pci_ad[31:0], pci_cbe_n[3:0],
pci_par, pci_frame_n, pci_trdy_n,
pci_irdy_n, pci_stop_n, pci_perr_n,
pci_serr_n, pci_devsel_n
Tdo pci_clk rising 2 7.5 2 7.5 2 7.5 ns
pci_req_n[0], pci_gnt_[2],
pci_gnt_n[1], pci_gnt_n[0],
pci_inta_n
Tdo pci_clk rising 2 7.5 2 7.5 2 7.5 ns
PCI for 2.5V Device
3
pci_ad[31:0], pci_par, pci_stop_n,
pci_perr_n, pci_serr_n,
pci_devsel_n, pci_lock_n
4
Tsu pci_clk rising 3 — 3 — 3 — ns
pci_cbe_n[3:0], pci_frame_n,
pci_trdy_n, pci_irdy_n
Tsu pci_clk rising 4 — 4 — 4 — ns
pci_idsel, pci_req_n[2],
pci_req_n[1], pci_req_n[0],
pci_gnt_n[0], pci_inta_n
Tsu pci_clk rising 5—5—5—ns
pci_gnt_n[0] Tsu pci_clk rising 5 — 5 — 5 — ns
pci_ad[31:0], pci_cbe_n[3:0],
pci_par, pci_frame_n, pci_trdy_n,
pci_irdy_n, pci_stop_n, pci_perr_n,
pci_serr_n, pci_devsel_n,
pci_lock_n
4
Thld pci_clk rising 0 — 0 — 0 — ns
pci_idsel, pci_req_n[2],
pci_req_n[1], pci_req_n[0],
pci_gnt_n[0], pci_inta_n
Thld pci_clk rising 0—0—0—ns
pci_eeprom_mdi Tsu pci_clk rising,
pci_eeprom_sk falling
15 — 12 — 10 — ns
pci_eeprom_mdi Thld pci_clk rising,
pci_eeprom_sk falling
15 — 12 — 10 — ns
pci_eeprom_mdo, pci-eeprom_cs Tdo pci_clk rising,
pci_eeprom_sk falling
—15—12—10 ns
pci_eeprom_sk Tdo pci_clk rising — 15 — 12 — 10 ns
Signal Symbol
Reference
Edge
RC32333
1
100MHz
RC32333
1
133MHz
RC32333
1
150MHz
Units
User Manual
Timing
Diagram
Reference
Min Max Min Max Min Max
Table 6 AC Timing Characteristics - RC32333 (Part 2 of 4)
17 of 30 May 4, 2004
IDT 79RC32333
pci_ad[31:0], pci_cbe_n[3:0],
pci_par, pci_frame_n, pci_trdy_n,
pci_irdy_n, pci_stop_n, pci_perr_n,
pci_serr_n, pci_devsel_n
Tdo pci_clk rising 2 7.5 2 7.5 2 7.5 ns
pci_req_n[0], pci_gnt_[2],
pci_gnt_n[1], pci_gnt_n[0],
pci_inta_n
Tdo pci_clk rising 2 7.5 2 7.5 2 7.5 ns
SDRAM Controller
sdram_245_dt_r_n Tdo8 cpu_masterclk rising — 15 — 12 — 10 ns Chapter 11,
Figures 11.4 and
11.5
sdram_ras_n, sdram_cas_n,
sdram_we_n, sdram_cs_n[3:0],
sdram_s_n[1:0],
sdram_bemask_n[3:0], sdram_cke
Tdo9 cpu_masterclk rising — 12 — 9 — 8 ns
sdram_addr_12 Tdo10 cpu_masterclk rising — 12 — 9 — 8 ns
sdram_245_oe_n Tdo11 cpu_masterclk rising — 12 — 9 — 8 ns
sdram_245_dt_r_n Tdoh4 cpu_masterclk rising 1 — 1 — 1 — ns
sdram_ras_n, sdram_cas_n,
sdram_we_n, sdram_cs_n[3:0],
sdram_s_n[1:0],
sdram_bemask_n[3:0] sdram_cke,
sdram_addr_12, sdram_245_oe_n
Tdoh4 cpu_masterclk rising 2.5 — 2.5 — 2.5 — ns
DMA
dma_ready_n[0], dma_done_n[0] Tsu7 cpu_masterclk rising 9 — 7 — 6 — ns
Chapter 13,
Figure 13.4
dma_ready_n[0], dma_done_n[0] Thld9 cpu_masterclk rising 1 — 1 — 1 — ns
Interrupt Handling
cpu_int_n[1:0], cpu_nmi_n Tsu9 cpu_masterclk rising 9 — 7 — 6 — ns Chapter 14,
Figure 14.12
cpu_int_n[1:0], cpu_nmi_n Thld13 cpu_masterclk rising 1 — 1 — 1 — ns
PIO
PIO[7:0] Tsu7 cpu_masterclk rising 9 — 7 — 6 — ns Chapter 15,
Figures 15.9 and
15.10
PIO[7:0] Thld9 cpu_masterclk rising 1 — 1 — 1 — ns
PIO[7:6], PIO[4:0] Tdo16 cpu_masterclk rising — 15 — 12 — 10 ns
PIO[5] Tdo19 cpu_masterclk rising — 15 — 12 — 10 ns
PIO[7:6], PIO[4:0] Tdoh7 cpu_masterclk rising 1 — 1 — 1 — ns
PIO[5] Tdoh7 cpu_masterclk rising 1 — 1 — 1 — ns
UARTs
uart_rx[0], uart_tx[0] Tsu7 cpu_masterclk rising 15 — 12 — 10 — ns
Chapter 17,
Figure 17.16
uart_rx[0], uart_tx[0] Thld9 cpu_masterclk rising 15 — 12 — 10 — ns
uart_rx[0], uart_tx[0] Tdo16 cpu_masterclk rising — 15 — 12 — 10 ns
uart_rx[0], uart_tx[0] Tdoh8 cpu_masterclk rising 1 — 1 — 1 — ns
Signal Symbol
Reference
Edge
RC32333
1
100MHz
RC32333
1
133MHz
RC32333
1
150MHz
Units
User Manual
Timing
Diagram
Reference
Min Max Min Max Min Max
Table 6 AC Timing Characteristics - RC32333 (Part 3 of 4)
18 of 30 May 4, 2004
IDT 79RC32333
Reset
mem_addr[19:17] Tsu10 cpu_coldreset_n rising 10 — 10 — 10 — ms Chapter 19,
Figures 19.8 and
19.9
mem_addr[19:17] Thld10 cpu_coldreset_n rising 1 — 1 — 1 — ns
mem_addr[22:20] Tsu22 cpu_masterclk rising 9 — 7 — 6 — ns
mem_addr[22:20] Thld22 cpu_masterclk rising 1 — 1 — 1 — ns
Debug Interface
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n, ejtag_pcst[2:0]
Tsu20 cpu_coldreset_n rising 10 — 10 — 10 — ms
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n, ejtag_pcst[2:0]
Thld20 cpu_coldreset_n rising 1 — 1 — 1 — ns Chapter 19,
Figure 19.9 and
Chapter 9,
Figure 9.2
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n
Tdo20 cpu_masterclk rising — 15 — 12 — 10 ns
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n
Tdoh20 cpu_masterclk rising 1 — 1 — 1 — ns
JTAG Interface
jtag_tms, jtag_tdi, jtag_trst_n
t
5
jtag_tck rising 10 — 10 — 10 — ns
See Figure 4
below.
jtag_tms, jtag_tdi, jtag_trst_n
t
6
jtag_tck rising 10 — 10 — 10 — ns
jtag_tdo
t
4
jtag_tck falling — 10 — 10 — 10 ns
EJTAG Interface
ejtag_tms
t
5
jtag_tclk rising 4 — 4 — 4 — ns
ejtag_tms
t
6
jtag_clk rising 2—2—2—ns
jtag_tdo Output Delay Time t
TDODO,
t
4
jtag_tck falling —6—6—6 ns
See Figure 4
below.
jtag_tdi Input Setup Time t
TDIS,
t
5
jtag_tck rising 4 — 4 — 4 — ns
jtag_tdi Input Hold Time t
TDIH,
t
6
jtag_tck rising 2 — 2 — 2 — ns
jtag_trst_n Low Time t
TRSTLow,
t
12
— 100 — 100 — 100 — ns
jtag_trst_n Removal Time t
TRSTR,
t
13
jtag_tck rising 3 — 3 — 3 — ns
ejtag_tpc Output Delay Time t
TPCDO,
t
8
ejtag_dclk rising -1 3 -1 3 -1 3 ns
ejtag_pcst Output Delay Time t
PCSTDO,
t
7
ejtag_dclk rising -1 3 -1 3 -1 3 ns
1.
At all pipeline frequencies.
2.
Guaranteed by design.
3.
This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2 at 33MHz.
4.
pci_rst_n is tested per PCI 2.2 as an asynchronous signal.
Signal Symbol
Reference
Edge
RC32333
1
100MHz
RC32333
1
133MHz
RC32333
1
150MHz
Units
User Manual
Timing
Diagram
Reference
Min Max Min Max Min Max
Table 6 AC Timing Characteristics - RC32333 (Part 4 of 4)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

IDT79RC32V333-100DHG

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IC MPU INTERPRISE 100MHZ 208QFP
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