FTLX3813M3xx Product Specification – August 2015
Finisar Corporation August 2015 Rev. D1 Page 10
• Register 76d, table 01h is a volatile memory. Therefore if the transceiver is
power-cycled, the register starts up with a value of 00h which corresponds to the
default Rx Threshold value.
• The threshold adjustment input value is 2’s complement 7 bit value (-128 to
+127), with 0 corresponding to default Rx threshold value. Full range of
adjustment provides at least a ±10% change in Rx threshold from the default
value.
8.5Gb/s Fibre-Channel rate select:
To operate the FTLX3813M3xx at 8.5Gb/s Fibre-Channel, the EEPROM-Table 0, Byte
117, Bit 0 must be set as follows;
• EEPROM Byte 117, Bit 0, value “1” for 8GFC:
• EEPROM Byte 117, Bit 0 value “0” for 10Gb/s rates:
o (It is also possible to bypass the CDRs with, Byte 111, Bit 0.)
By default, a power cycling the transceiver will return the transceiver to normal 10Gb/s
operation with the CDRs active.
IX. Mechanical Specifications
Finisar’s XFP transceivers are compliant with the dimensions defined by the XFP Multi-
Sourcing Agreement (MSA).
XFP Transceiver (dimensions are in mm)
