8-BIT LVDS RECEIVER FOR VIDEO
V386
V386 Datasheet 4 10/20/04 Revision 1.7
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
Note: The skew margins mean the maximum timing tolerance between the clock and data channel when
the receiver still works well. This margin takes into acount the receiver input setup and hold time, and
internal clock jitter (i.e., internal data sampling window - RSPos). Thyis margin allows for LVDS transmitter
pulse position, interconnect skew, inter-symbol interference and intrinsic channel mismatch which will
cause the skew between clock (RC+ and RCK-) and data (RX[n]+ and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
CMOS Low-to-High Transition Time
for Clock
CLHT 20% to 80% VCC 2 6 ns
CMOS Low-to-High Transition Time
for Clock
CHLT 80% to 20% VCC 1.8 6 ns
CLKOUT period RCOP 11.76 40 ns
CLKOUT High Time RCOH At 2.0 V 4.5 5 25 ns
CLKOUT Low Time RCOL At 0.8 V 4 5 25 ns
Data Setup to CLKOUT RSRC At 2.0 V 3.5 ns
Data Hold to CLKOUT RHRC At 0.8 V 3.5 ns
RCK+/- to CLKOUT Delay RCCD At 85 MHz 5.5 7 9.5 ns
Receiver PLL Setup Time RPLLS 10 ms
Receiver Power Down Delay RPDD 10 µs
Receiver Input Strobe Position for
Bit0
RSPos0 At 85 MHz, T = 11.76 ns 0.49 0.84 1.19 ns
Receiver Input Strobe Position for
Bit1
RSPos1 At 85 MHz, T = 11.76 ns 2.17 2.52 2.87 ns
Receiver Input Strobe Position for
Bit2
RSPos2 At 85 MHz, T = 11.76 ns 3.85 4.2 4.55 ns
Receiver Input Strobe Position for
Bit3
RSPos3 At 85 MHz, T = 11.76 ns 5.53 5.88 6.23 ns
Receiver Input Strobe Position for
Bit4
RSPos4 At 85 MHz, T = 11.76 ns 7.21 7.56 7.91 ns
Receiver Input Strobe Position for
Bit5
RSPos5 At 85 MHz, T = 11.76 ns 8.89 9.24 9.59 ns
Receiver Input Strobe Position for
Bit6
RSPos6 At 85 MHz, T = 11.76 ns 10.57 10.92 11.27 ns
RxIn Skew Margin (see note and
Figure 8)
Rskm At 85 MHz, T = 11.76 ns 300 ps
At 65 MHz, T = 15.38 ns 500 ps
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to Ambient θ
JA
Still air 84 °C/W
θ
JA
1 m/s air flow 76 °C/W
θ
JA
3 m/s air flow 67 °C/W
Thermal Resistance Junction to Case θ
JC
50 °C/W
Parameter Symbol Conditions Min. Typ. Max. Units
8-BIT LVDS RECEIVER FOR VIDEO
V386
V386 Datasheet 5 10/20/04 Revision 1.7
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
Timing Diagrams
Figure 1a. “Worst Case” Test Pattern
Figure 1b. 16-Grayscale Test-Pattern Waveforms
Figure 2. V386 CMOS/TTL Output Load and Transition Time
CLKIN/CLKOUT
T
ODD Data In/Data Out
EVEN Data In/Data Out
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4-7, 12-15, 20-23
D24-27
8 pF
CMOS/TTL Output
DLHT
20%
20%
80% 80%
DLHT
8-BIT LVDS RECEIVER FOR VIDEO
V386
V386 Datasheet 6 10/20/04 Revision 1.7
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com
Figure 3. V386 SETUP/HOLD and High/Low Times
CLKOUT
D0 – D27 Out
0.8 V
2.0 V
RCOP
2.0 V
2.0 V
0.8 V
RCOH RCOL
RSRC
RHRC
2.0 V
SETUP
2.0 V
HOLD

V386GT

Mfr. #:
Manufacturer:
Description:
IC RCVR 8BIT LVDS VID 56-TSSOP
Lifecycle:
New from this manufacturer.
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