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CSPUA877ABVG8

P1-P3P4-P6P7-P9P10-P12P13-P14
10
COMMERCIAL TEMPERATURE RANGE
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Period jitter
Half-Period jitter
TEST CIRCUIT AND SWITCHING WAVEFORMS
NOTE:
fo = Average input frequency measured at CLK / CLK
NOTE:
fo = Average input frequency measured at CLK / CLK
Yx, FBOUT
Yx, FBOUT
tjit(per)
=
tcycle n
1
f
o
Yx, FBOUT
Yx, FBOUT
tcycle n
1
f
o
Yx, FBOUT
Yx, FBOUT
1
f
o
tjit(hper)
=
thalf period n
1
2*f
o
Yx, FBOUT
Yx, FBOUT
thalf pe riod n
thalf period n+1
11
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
Dynamic Phase Offset
Time Delay Between Output Enable (OE) and Clock Output (Y, Y)
OE
Y/Y
OE
50% V
DDQ
tEN
50% VDDQ
50% VDDQ
tDIS
50% VDDQ
Y
Y
Y
Y
FBIN
CLK
t(Ø)DYN
t(Ø)
t(Ø)DY N
SSC ON
SSC OFF
CLK
FBIN
t(Ø)DYN
t(Ø)
t(Ø)DYN
SSC ON
SSC OFF
12
COMMERCIAL TEMPERATURE RANGE
IDTCSPUA877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Input and Output Slew Rates
APPLICATION INFORMATION
Clock Loading on the PLL outputs (pF)
Clock Structure # of SDRAM Loads per Clock Min. Max.
#1 2 3 5
#2 4 6 10
TEST CIRCUIT AND SWITCHING WAVEFORMS
Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ)
NOTES:
Place all decoupling capacitors as close to the CSPUA877A pins as possible.
Use wide traces for AVDD and AGND.
Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz).
VDDQ
GND
VIA
CARD
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
AVDD
AGND
V
DDQ
GND
CSPUA877A
1Ω
1
0.1uF
0603
10
Clock Inputs and
Outputs, OE
80%
20%
V
ID,VOD
tR(I), tR(O)
80%
20%
V20%
V80%
tSLF(I/O)
=
tF(I/O)
tF(I), tF(O)
V20%
V80%
tSLR(I/O)
=
tR(I/O)
P1-P3P4-P6P7-P9P10-P12P13-P14

CSPUA877ABVG8

Mfr. #:
Buy CSPUA877ABVG8
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1.8V PLL Differ 1:10 DDR2 667/800 Clk Dvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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