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9LPRS502SKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
10
MLF Pin Description (Continued)
PIN # PIN NAME TYPE DESCRIPTION
43 VDDSRC_IO PWR Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
44 CPUC2_ITP/SRCC8 OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
45 CPUT2_ITP/SRCT8 OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
46 NC NC Not Connected
47 VDDCPU_IO PWR Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
48 CPUC1_F OUT Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
49 CPUT1_F O UT True c lock of low power differential CPU clock pair. This cloc k will be free-running during iAMT.
50 GNDCPU PWR Ground Pin for CPU Outputs
51 CPUC0 OUT Complement clock of low power differential CPU clock pair.
52 CPUT0 OUT True clock of low power differential CPU clock pair.
53 VDDCPU PWR Power Supply 3.3V nominal.
54 CK_PWRGD/PD# IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
55 FSLB/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer
to Test Clarification Table.
56 GNDREF PWR Ground pin for crystal oscillator circ uit
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
11
Funtional Block Diagram
Power Groups
General Description
ICS9LPRS502 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for
next generation Intel processors and Intel chipsets. ICS9LPRS502 is driven with a 14.318MHz crystal. It also provides a
tight ppm accuracy output for Serial ATA and PCI-Express support.
REF
CPU(1:0)
CPU PLL1
SS
OSC
REF
SRC(7:3)
PLL2
Non-SS
PLL3
SS
7
SRC8/ITP
PCI(5:0)
SRC2/SATA
SRC1/SE(2:1)
SE Outputs
S ATA
DOT96MHz
PCI33MHz
SRC
SRC
S
R
C
_
M
A
I
N
PCI33MHz
Differential Output
SRC0/DOT96
48MHz
48MHz
CPU
FSLA
CKPWRGD/PD#
PCI_STOP#
CPU_STOP#
CR#_(A:F)
SRC5_EN
ITP_EN
FSLC/TESTSEL
FSLB/TESTMODE
Control
Logic
X1
X2
VDD GND
41 44 CPUCLK Low power outputs
47 44
26, 37 23,34 Low power outputs
31 23,34 PLL 1
20 19 Low power outputs
16 19 PLL 3
12 11 DOT 96Mhz Low power outputs
911
53 50
28
USB 48
Xtal, REF
PCICLK
SRCCLK
Pin Number
Description
PLL3/SE
Master Clock, Analog
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
12
Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V 1,7
Maximum Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 3.8 V 1,7
Maximum Input Voltage V
IH
3.3V LVCMOS Inputs 4.6 V 1,7,8
Minimum Input Voltage V
IL
Any Input GND - 0.5 V 1,7
Storage Temperature Ts - -65 150
°
C1,7
Input ESD protection ESD prot Human Body Model 2000 V 1,7
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes
Ambient Operating Temp Tambient - 0 70 °C 1
Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1
Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 1.05 3.465 V 1
Input High Voltage V
IHSE
Single-ended inputs 2 V
DD
+ 0.3 V 1
Input Low Voltage V
ILSE
Single-ended inputs V
SS
- 0.3 0.8 V 1
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Leakage Current I
INRES
Inputs with pull or pull down
resistors
V
IN
= V
DD ,
V
IN
=
GND
-200 200 uA 1
Output High Voltage V
OHS E
Single-ended outputs, I
OH
= -1mA 2.4 V 1
Output Low Voltage V
OLS E
Single-ended outputs, I
OL
= 1 mA 0.4 V 1
Output High Voltage V
OHDIF
Differential Outputs 0.7 0.9 V 1
Output Low Voltage V
OLDI
F
Differential Outputs 0.4 V 1
Low Threshold Input-
High Voltage (Test Mode)
V
IH_FS_TEST
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5% 0.7 1.5 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
I
DD_DEFAULT
3.3V supply, PLL3 off 250 mA 1
I
DD_PLL3DIF
3.3V supply, PLL3 Differential Out 250 mA 1
I
DD_PLL3SE
3.3V supply, PLL3 Single-ended
Out
250 mA 1
I
DD_IO
0.8V supply, Differential IO current,
all outputs enabled
25 80 mA 1
I
DD_PD3.3
3.3V supply, Power Down Mode 10 mA 1
I
DD_PDIO
0.8V IO supply, Power Down Mode 0.1 mA 1
I
DD_iAMT3.3
3.3V supply, iAMT Mode 26 mA 1
I
DD_iAMT0.8
0.8V IO supply, iAMTMode 8 mA 1
Input Frequency F
i
V
DD
= 3.3 V 15 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 1.5 5 pF 1
C
OU
T
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 6 pF 1
Spread Spectrum Modulation
Frequency
f
SSMOD
Triangular Modulation 30 33 kHz 1
Operating Supply Current
Power Down Current
iAMT Mode Current
Input Capacitance
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

9LPRS502SKLF

Mfr. #:
Buy 9LPRS502SKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
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