ADCMP391/ADCMP392/ADCMP393 Data Sheet
Rev. D | Page 10 of 17
THEORY OF OPERATION
BASIC COMPARATOR
In its most basic configuration, a comparator can be used to
convert an analog input signal to a digital output signal (see
Figure 26). The analog signal on INx+ is compared to the
voltage on INx−, and the voltage at OUTx is either high or low,
depending on whether INx+ is at a higher or lower potential
than INx−, respectively.
OUTx
V
IN
V
REF
INx+
INx–
V
CC
V+
V+
V
REF
V
IN
V
OUT
0V
t
12206-226
Figure 26. Basic Comparator and Input and Output Signals
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonRRI stage (that is, a single differential pair)
limits the input voltage to approximately one gate-to-source
voltage (V
GS
) away from one of the supply lines. Because V
GS
for
normal operation is commonly more than 1 V, a single differential
pair input stage comparator greatly restricts the allowable input
voltage. This restriction can be quite limiting with low voltage
supplies. To resolve this issue, RRI stages allow the input signal
range to extend up to the supply voltage range. In the case of the
ADCMP391/ADCMP392/ADCMP393, the inputs continue to
operate 200 mV beyond the supply rails.
OPEN-DRAIN OUTPUT
The ADCMP391/ADCMP392/ADCMP393 have an open-drain
output stage that requires an external resistor to pull up to the
logic high voltage level when the output transistor is switched
off. The pull-up resistor must be large enough to avoid excessive
power dissipation, but small enough to switch logic levels
reasonably quickly when the comparator output is connected to
other digital circuitry. The rise time of the open-drain output
depends on the pull-up resistor (R
PULLUP
) and load capacitor (C
L
)
used.
The rise time can be calculated by
t
R
= 2.2 R
PULLUP
C
L
(1)
POWER-UP BEHAVIOR
On power-up, when V
CC
reaches 0.9 V, the ADCMP391/
ADCMP392/ADCMP393 is guaranteed to assert an output low
logic. When the voltage on the V
CC
pin exceeds UVLO, the
comparator inputs take control.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type of architecture, in both op amps
and comparators, have a dual front-end design. PMOS devices
are inactive near the V
CC
rail, and NMOS devices are inactive near
GND. At some predetermined point in the common-mode range, a
crossover occurs. At this point, normally 0.8 V and V
CC
− 0.8 V, the
measured offset voltages change.
COMPARATOR HYSTERESIS
In noisy environments, or when the differential input amplitudes
are relatively small or slow moving, adding hysteresis (V
HYS
) to
the comparator is often desirable. The transfer function for a
comparator with hysteresis is shown in Figure 27. As the input
voltage approaches the threshold (0 V in Figure 27) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
HYS
/2. The
new switch threshold becomes −V
HYS
/2. The comparator remains
in the high state until the −V
HYS
/2 threshold is crossed from
below the threshold region in a negative direction. In this
manner, noise or feedback output signals centered on the 0 V
input cannot cause the comparator to switch states unless it
exceeds the region bounded by ±V
HYS
/2.
OUTPUT
INPUT
0V
V
OL
V
OH
+V
HYST
2
–V
HYST
2
12206-227
Figure 27. Comparator Hysteresis Transfer Function
