XRA1206IL16MTR-F Datasheet XRA1206IL16-F, XRA1206IG16-0A-EB, XRA1206IG16-F | P4-P6

XRA1206

8-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0

1.0 FUNCTIONAL DESCRIPTIONS

1.1 I

C-bus Interface

The I

C-bus interface is compliant with the Standard-mode and Fast-mode I

C-bus specifications. The I

C-bus

interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock

and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400

kbps.

The first byte sent by an I

C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is

HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that

contains the address of the register to access. The XRA1206 responds to each write with an acknowledge

(SDA driven LOW by XRA1206 for one clock cycle when SCL is HIGH). The last byte sent by an I

C-bus

master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See

Figures 3 - 5 below.

For complete details, see the I

C-bus specifications.

FIGURE 3. I C START AND STOP CONDITIONS

SDA

SCL

START condition

STOP condition

FIGURE 4. MASTER WRITES TO SLAVE

SWA A AP

SLAVE

ADDRESS

COMMAND

BYTE

DATA

BYTE

White block: host to XRA120x

Grey block: XRA120x to host

FIGURE 5. MASTER READS FROM SLAVE

SWA AR

SLAVE

ADDRESS

COMMAND

BYTE

White block: host to XRA120x

Grey block: XRA120x to host

SLAVE

ADDRESS

nDATA ANAPLAST DATA

XRA1206

REV. 1.0.0 8-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS

1.1.1 I

C-bus Addressing

There could be many devices on the I

C-bus. To distinguish itself from the other devices on the I

C-bus, the

XRA1206 has up to 4 I

C slave addresses using the A0 address line. Table 1 below shows the different

addresses that can be selected.

TABLE 1: I C ADDRESS MAP

C ADDRESS

GND 0x40 (0100 000X)

VCC 0x42 (0100 001X)

SCL 0x50 (0101 000X)

SDA 0x52 (0101 001X)

1.1.2 I

C Read and Write

A read or write transaction is determined by bit-0 of the slave address. If bit-0 is ’0’, then it is a write

transaction. If bit-0 is ’1’, then it is a read transaction.

1.1.3 I

C Command Byte

An I

C command byte is sent by the I

C master following the slave address. The command byte indicates the

address offset of the register that will be accessed.

Table 2 below lists the command bytes for each register.

TABLE 2: I C COMMAND BYTE (REGISTER ADDRESS)

COMMAND BYTE REGISTER NAME DESCRIPTION READ/WRITE DEFAULT VALUES

0x00 GSR - GPIO State Read-Only 0xXX

0x01 OCR - Output Control Read/Write 0xFF

0x02 PIR - Input Polarity Inversion Read/Write 0x00

0x03 GCR - GPIO Configuration Read/Write 0xFF

0x04 PUR - Input Internal Pull-up Resistor Enable/Disable Read/Write 0x00

0x05 IER - Input Interrupt Enable Read/Write 0x00

0x06 TSCR - Output Three-State Control Read/Write 0x00

0x07 ISR - Input Interrupt Status Read 0x00

0x08 REIR - Input Rising Edge Interrupt Enable Read/Write 0x00

0x09 FEIR - Input Falling Edge Interrupt Enable Read/Write 0x00

0x0A IFR - Input Filter Enable/Disable Read/Write 0xFF

XRA1206

8-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0

1.2 Interrupts

The table below summarizes the interrupt behavior of the different register settings for the XRA1206.

TABLE 3: INTERRUPT GENERATION AND CLEARING

BIT BIT BIT BIT BIT

INTERRUPT GENERATED BY: INTERRUPT CLEARED BY:

1 0 X X X No interrupts enabled (default) N/A

1 1 0 0

0 A rising or falling edge on the input Reading the GSR register or if the input

changes back to its previous state (state of

input during last read to GSR)

1 A rising or falling edge on the input and

remains in the new state for more than

1075ns

1 1 1 0

0 A rising edge on the input Reading the GSR register

1 A rising edge on the input and remains high

for more than 1075ns

1 1 0 1

0 A falling edge on the input Reading the GSR register

1 A falling edge on the input and remains low

for more than 1075ns

1 1 1 1

0 A rising or falling edge on the input Reading the GSR register

1 A rising or falling edge on the input and

remains in the new state for more than

1075ns

0 x x x x No interrupts in output mode N/A

GCR IER REIR FEIR IFR

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

XRA1206IL16MTR-F

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