Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. C1
12/18/2016
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61C5128AL/AS
IS64C5128AL/AS
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speedaccesstime:10ns,12ns
• LowActivePower:150mW(typical)
• LowStandbyPower:10mW(typical)
CMOS standby
LOWPOWER:(IS61/64C5128AS)
• High-speedaccesstime:25ns
• LowActivePower:75mW(typical)
• LowStandbyPower:1mW(typical)
CMOS standby
• TTLcompatibleinterfacelevels
• Single5V±10%powersupply
• Fullystaticoperation:noclockorrefresh
required
• Availablein36-pinSOJ(400-mil),32-pin
sTSOP-I,32-pinSOP,44-pinTSOP-IIand32-pin
TSOP-IIpackages
• Commercial,IndustrialandAutomotivetempera-
ture ranges available
• Lead-freeavailable
DESCRIPTION
TheISSIIS61C5128AL/ASandIS64C5128AL/ASarehigh-
speed, 4,194,304-bit static RAMs organized as 524,288
words by 8 bits. They are fabricated using ISSI's high-
performanceCMOStechnology.Thishighlyreliableprocess
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE.Theactive LOW
WriteEnable(WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
TheIS61C5128AL/ASandIS64C5128AL/ASarepackaged
intheJEDECstandard36-pinSOJ(400-mil),32-pinsTSOP-I,
32-pinSOP,44-pinTSOP-IIand32-pinTSOP-IIpackages
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2016
512K x 8 HIGH-SPEED CMOS STATIC RAM
A0-A18
CE
OE
WE
512K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
