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74ABT374CMSAX

P1-P3P4-P6P7-P9P10-P12P13-P13
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT374 Rev. 1.5.0
December 2007
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
■
Edge-triggered D-type inputs
■
Buffered positive edge-triggered clock
■
3-STATE outputs for bus-oriented applications
■
Output sink capability of 64mA, source capability of
32mA
■
Guaranteed output skew
■
Guaranteed multiple output switching specifications
■
Output switching specified for both 50pF and 250pF
loads
■
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■
Guaranteed latchup protection
■
High-impedance, glitch-free bus loading during entire
power up and power down cycle
■
Nondestructive, hot-insertion capability
General Description
The ABT374 is an octal D-type flip-flop featuring sepa-
rate D-type inputs for each flip-flop and 3-STATE outputs
for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE
) are common to all flip-flops.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74ABT374CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
74ABT374CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT374 Rev. 1.5.0 2
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram Pin Descriptions
Functional Description
The ABT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE
) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When OE
is HIGH, the outputs are in a high impedance
state. Operation of the OE
input does not affect the state
of the flip-flops.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Pin Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input (Active Rising Edge)
OE
3-STATE Output Enable Input
(Active LOW)
O
0
–O
7
3-STATE Outputs
Inputs Internal Outputs
FunctionOE CP D Q O
H H L NC Z Hold
H H H NC Z Hold
H L L Z Load
H H H Z Load
L L L L Data Available
L H H H Data Available
L H L NC NC No Change in
Data
L H H NC NC No Change in
Data
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ABT374 Rev. 1.5.0 3
74ABT374 — Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
T
STG
Storage Temperature –65°C to +150°C
T
A
Ambient Temperature Under Bias –55°C to +125°C
T
J
Junction Temperature Under Bias –55°C to +150°C
V
CC
V
CC
Pin Potential to Ground Pin –0.5V to +7.0V
V
IN
Input Voltage
(1)
–0.5V to +7.0V
I
IN
Input Current
(1)
–30mA to +5.0mA
V
O
Voltage Applied to Any Output
Disabled or Power-Off State
HIGH State
–0.5V to 5.5V
–0.5V to V
CC
Current Applied to Output in LOW State (Max.) twice the rated I
OL
(mA)
DC Latchup Source Current Across Common Operating Range
OE
Pin
Other Pins
–150mA
–500mA
Over Voltage Latchup (I/O) 10V
Symbol Parameter Rating
T
A
Free Air Ambient Temperature –40°C to +85°C
V
CC
Supply Voltage +4.5V to +5.5V
∆
V
/
∆
t Minimum Input Edge Rate
Data Input
Enable Input
Clock Input
50mV/ns
20mV/ns
100mV/ns
P1-P3P4-P6P7-P9P10-P12P13-P13

74ABT374CMSAX

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Description:
IC FF D-TYPE SNGL 8BIT 20SSOP
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