Document Number: 38-05132 Rev. *I Page 6 of 14
Switching Characteristics
Over the Operating Range
[5]
Parameter Description
-8 -10 -12 -15
Unit
Min Max Min Max Min Max Min Max
Read Cycle
t
power
[6]
V
CC
(Typical) to the First Access 100 100 100 100 μs
t
RC
Read Cycle Time 8 10 12 15 ns
t
AA
Address to Data Valid 8 10 12 15 ns
t
OHA
Data Hold from Address Change3333ns
t
ACE
CE LOW to Data Valid 8 10 12 15 ns
t
DOE
OE LOW to Data Valid 5567ns
t
LZOE
OE LOW to Low Z
[7]
0000ns
t
HZOE
OE HIGH to High Z
[7, 8]
4567ns
t
LZCE
CE LOW to Low Z
[7]
3333ns
t
HZCE
CE HIGH to High Z
[7, 8]
4567ns
t
PU
[9]
CE LOW to Power Up0000ns
t
PD
[9]
CE HIGH to Power Down 8 10 12 15 ns
t
DBE
Byte Enable to Data Valid 5567ns
t
LZBE
Byte Enable to Low Z0000ns
t
HZBE
Byte Disable to High Z 4567ns
Write Cycle
[10]
t
WC
Write Cycle Time 8 10 12 15 ns
t
SCE
CE LOW to Write End 7 8 9 10 ns
t
AW
Address Setup to Write End 7 8 9 10 ns
t
HA
Address Hold from Write End0000ns
t
SA
Address Setup to Write Start0000ns
t
PWE
WE Pulse Width 6 7 8 10 ns
t
SD
Data Setup to Write End5568ns
t
HD
Data Hold from Write End0000ns
t
LZWE
WE HIGH to Low Z
[7]
3333ns
t
HZWE
WE LOW to High Z
[7, 8]
4567ns
t
BW
Byte Enable to End of Write6789ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
6. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
7. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 5. Transition is measured ±500
mV from steady state voltage.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE
LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The
transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
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