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CY2412SXC-3T

P1-P3P4-P5
CY2412
MPEG Clock Generator with VCXO
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07227 Rev. *F Revised June 05, 2008
Features
■ Integrated phase-locked loop (PLL)
■ Low-jitter, high-accuracy outputs
■ VCXO with analog adjust
■ 3.3V operation
■ 8-pin SOIC package
Benefits
■ Highest-performance PLL tailored for multimedia applications
■ Meets critical timing requirements in complex system designs
■ Large ± 150-ppm range, better linearity
■ Enables application compatibility
Pin Configuration
Figure 1. CY2412, 8-Pin SOIC
Part Number Outputs Input Frequency Range Output Frequencies VCXO Profile
CY2412-1 3 13.5-MHz pullable crystal input per
Cypress specification
Two 27 MHz outputs, one 54 MHz (3.3V) Linear
CY2412-3 3 13.5-MHz pullable crystal input per
Cypress specification
27 MHz, 13.5 MHz, 54 MHz (3.3V) Linear
13.5 XIN
XOUT
CLKC
OUTPUT
DIVIDERS
PLL
OSC
VCXO
CLKA
Q
P
VCO
VDD
VSS
Φ
CLKB
Logic Block Diagram
1
2
3
4
XOUT
XIN
VCXO
CLKA
VSS
CLKC
CLKB
5
6
7
8
VDD
Table 1. Pin Definition - CY2412, 8-Pin SOIC
Pin Name Pin Number Pin Description
X
IN
1 Reference Crystal Input
V
DD
2 Voltage Supply
VCXO 3 Input Analog Control for VCXO
V
SS
4 Ground
CLKA 5 54-MHz clock output
CLKB 6 13.5-MHz clock output
CLKC 7 27-MHz clock output
X
OUT
[2]
8 Reference Crystal Output
[+] Feedback
CY2412
Document #: 38-07227 Rev. *F Page 2 of 5
Absolute Maximum Conditions
Recommended Operating Conditions
Pullable Crystal Specifications
[1]
Parameter Description Condition Min Typ. Max Unit
F
NOM
Nominal crystal frequency Parallel resonance, fundamental
mode, AT cut
– 13.5 – MHz
C
LNOM
Nominal load capacitance – 14 – pF
R
1
Equivalent series resistance (ESR) Fundamental mode – – 25 Ω
R
3
/R
1
Ratio of third overtone mode ESR to funda-
mental mode ESR
Ratio used because typical R
1
values are much less than the
maximum spec.
3––
DL Crystal drive level No external series resistor as-
sumed
–0.52.0mW
F
3SEPHI
Third overtone separation from 3*F
NOM
High side 300 – – ppm
F
3SEPLO
Third overtone separation from 3*F
NOM
Low side – – –150 ppm
C
0
Crystal shunt capacitance – – 7 pF
C
0/
C
1
Ratio of shunt to motional capacitance 180 – 250
C
1
Crystal motional capacitance 14.4 18 21.6 pF
Parameter Description Min Max Unit
V
DD
Supply Voltage –0.5 7.0 V
T
S
Storage Temperature
[3]
–65 125 °C
T
J
Junction Temperature – 125 °C
Digital Inputs V
SS
– 0.3 V
DD
+ 0.3 V
Digital Outputs referred to V
DD
V
SS
– 0.3 V
DD
+ 0.3 V
Electrostatic Discharge 2 kV
Parameter Description Min Typ. Max Unit
V
DD
Operating Voltage 3.14 3.3 3.47 V
T
A
Ambient Temperature 0 70 °C
C
LOAD
Max. Load Capacitance 15 pF
f
REF
Reference Frequency 13.5 MHz
t
PU
Power up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
0.05 500 ms
Notes
1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
2. Float X
OUT
if X
IN
is externally driven.
3. Rated for ten years.
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ. Max Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
= 3.3V 12 24 mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
= 3.3V 12 24 mA
C
IN
Input Capacitance 7pF
I
IZ
Input Leakage Current 5 μA
[+] Feedback
CY2412
Document #: 38-07227 Rev. *F Page 3 of 5
AC Electrical Characteristics
Figure 2. Duty Cycle Definition; DC = t2/t1
Figure 3. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4
Figure 4. Test Circuit
f
ΔXO
VCXO pullability range +150 ppm
V
VCXO
VCXO input range 0 V
DD
V
f
VBW
VCXO input bandwidth DC to
200
kHz
I
DD
Supply Current Sum of Core and Output Current 35 mA
DC Electrical Characteristics (continued)
Parameter Description Test Conditions Min Typ. Max Unit
Parameter
[4]
Description Test Conditions Min Typ. Max Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 2, 50% of V
DD
45 50 55 %
ER Rising Edge Rate Clock Edge Rate, Measured from 20% to 80% of V
DD,
C
LOAD
= 15 pF. See Figure 3.
0.8 1.4 V/ns
EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20%
of V
DD,
C
LOAD
= 15 pF. See Figure 3.
0.8 1.4 V/ns
t
9
Clock Jitter Peak to Peak period jitter 100 200 ps
t
10
PLL Lock Time 3ms
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
Notes
4. Not 100% tested.
[+] Feedback
P1-P3P4-P5

CY2412SXC-3T

Mfr. #:
Buy CY2412SXC-3T
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK GEN MPEG W/VCXO 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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