CY22392FC Datasheet CY22392FC | P4-P6

CY22392

Document #: 38-07013 Rev. *F Page 4 of 9

Improving Jitter

Jitter Optimization Control is useful in mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning,

enabling superior jitter performance.

Power Supply Sequencing

For parts with multiple V

pins, there are no power supply

sequencing requirements. The part is not fully operational until

all V

pins have been brought up to the voltages specified in

the Operating Conditions table. All grounds must be connected

to the same ground plane.

CyberClocks™ Software

The CyberClocks application enables users to configure this

device. Within CyberClocks, select the CyClocksRT tool. The

easy-to-use interface offers complete control of the many

features of this family including input frequency, PLL, output

frequencies, and different functional options. Data sheet

frequency range limitations are checked and performance tuning

is automatically applied. CyClocksRT also has a power

estimation feature that enables you to see the power

consumption of your specific configuration. Download a copy of

CyberClocks free on Cypress’s web site at www.cypress.com.

Install and run it on any PC running Windows.

Device Programming

Part numbers starting with CY22392F are ‘field programmable’

devices. Field programmable devices are shipped

unprogrammed, and must be programmed prior to installation on

a PCB. After a programming file (.jed) is created using

CyberClocks software, devices can be programmed in small

quantities using the CY3672 programmer and CY3698 adapter.

Volume programming is available through Cypress

Semiconductor’s value added distribution partners or by using

third party programmers from BP Microsystems, HiLo Systems,

and others. For sufficiently large volumes, Cypress can supply

pre-programmed devices with a part number extension that is

configuration-specific.

Junction Temperature Limitations

It is possible to program the CY22392 such that the maximum

junction temperature rating is exceeded. The package θ

115 C/W. Use the CyClocksRT power estimation feature to verify

that the programmed configuration meets the junction

temperature and package power dissipation maximum ratings.

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Supply Voltage................................................–0.5V to +7.0V

DC Input Voltage ........................... –0.5V to + (AV

+ 0.5V)

Storage Temperature ................................. –65°C to +125°C

Junction Temperature.................................................. 125°C

Data Retention at Tj = 125°C .................................>10 years

Maximum Programming Cycles........................................100

Package Power Dissipation...................................... 350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................... 2000V

Latch up (according to JEDEC 17)...................... >

±200 mA

Operating Conditions

The following table lists the recommended operating conditions.

[1]

Parameter Description Min Typ Max Unit

/AV

Supply Voltage 3.135 3.3 3.465 V

Commercial Operating Temperature, Ambient 0 – +70 °C

Industrial Operating Temperature, Ambient –40 – +85 °C

LOAD_OUT

Maximum Load Capacitance – – 15 pF

REF

External Reference Crystal 8 – 30 MHz

External Reference Clock

[2]

, Commercial

1 – 166 MHz

External Reference Clock

[2]

, Industrial

1 – 150 MHz

Power up time for all VDD's to reach minimum specified voltage

(power ramps must be monotonic)

0.05 – 500 ms

Notes

1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

2. External input reference clock must have a duty cycle between 40% and 60%, measured at V

/2.

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CY22392

Document #: 38-07013 Rev. *F Page 5 of 9

Electrical Characteristics

Parameter Description Conditions Min Typ Max Unit

Output High Current

[3]

– 0.5, V

=3.3V 12 24 – mA

Output Low Current

[3]

= 0.5V, V

=3.3V 12 24 – mA

XTAL_MIN

Crystal Load Capacitance

[3]

Capload at minimum setting – 6 – pF

XTAL_MAX

Crystal Load Capacitance

[3]

Capload at maximum setting – 30 – pF

LOAD_IN

Input Pin Capacitance

[3]

Except crystal pins – 7 – pF

High Level Input Voltage CMOS levels,% of AV

70% – – AV

Low Level Input Voltage CMOS levels,% of AV

––30%AV

Input High Current V

=AV

–0.3V – <1 10 μA

Input Low Current V

=+0.3V – <1 10 μA

Output Leakage Current Three-state outputs – 10 μA

Total Power Supply Current 3.3V Power Supply; 2 outputs at

166 MHz; 4 outputs at 83 MHz

–100–mA

3.3V Power Supply; 2 outputs at

20 MHz; 4 outputs at 40 MHz

–50–mA

DDS

Total Power Supply Current in

Shutdown Mode

Shutdown active – 5 20 μA

Switching Characteristics

Parameter Name Description Min Typ Max Unit

1/t

Output Frequency

[3, 4]

Clock output limit, Commercial – – 200 MHz

Clock output limit, Industrial – – 166 MHz

Output Duty Cycle

[3, 5]

Duty cycle for outputs, defined as t

÷ t

Fout < 100 MHz, divider >= 2, measured at V

45% 50% 55%

Duty cycle for outputs, defined as t

÷ t

Fout > 100 MHz or divider = 1, measured at V

40% 50% 60%

Rising Edge Slew Rate

[3]

Output clock rise time, 20% to 80% of V

0.75 1.4 – V/ns

Falling Edge Slew

Rate

[3]

Output clock fall time, 80% to 20% of V

0.75 1.4 – V/ns

Output three-state

Timing

[3]

Time for output to enter or leave three-state mode

after SHUTDOWN

/OE switches

– 150 300 ns

Clock Jitter

[3, 6]

Peak-to-peak period jitter, CLK outputs measured

at V

–400–ps

Lock Time

[3]

PLL Lock Time from Power up – 1.0 3 ms

Notes

3. Guaranteed by design, not 100% tested.

4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.

5. Reference Output duty cycle depends on XTALIN duty cycle.

6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.

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CY22392

Document #: 38-07013 Rev. *F Page 6 of 9

Test Circuit

Switching Waveforms

Figure 2. All Outputs, Duty Cycle, and Rise/Fall Time

Figure 3. Output Three-State Timing

Figure 4. CLK Output Jitter

Figure 5. Frequency Change

OUTPUT

ALL

OUTPUTS

THREE-STATE

CLK

OUTPUT

SELECT

OLD SELECT NEW SELECT STABLE

old

new

OUTPUT

0.1

CLK out

LOAD

GND

OUTPUTS

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P1-P3 P4-P6 P7-P9

CY22392FC

Mfr. #:

Buy CY22392FC

Manufacturer:

Cypress Semiconductor

Description:

IC CLKSYN FLSH PROG 3PLL 16TSSOP

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CY22392FC