Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
82
t
LLAX
ALE
PSEN
PORT 0
PORT 2
WR
A0–A7
FROM RI OR DPL
DATA OUT A0–A7 FROM PCL INSTR IN
P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH
t
WHLH
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
SU00026
Figure 59. External Data Memory Write Cycle
012345678
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
SET TI
SET RI
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
SU00027
1230 4567
VALID VALID VALID VALID VALID VALID VALID VALID
Figure 60. Shift Register Mode Timing
V
CC
–0.5
0.45V
0.7V
CC
0.2V
CC
–0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
SU00009
Figure 61. External Clock Drive
Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
83
V
CC
–0.5
0.45V
0.2V
CC
+0.9
0.2V
CC
–0.1
NOTE:
AC inputs during testing are driven at V
CC
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V
IH
min for a logic ‘1’ and V
IL
max for a logic ‘0’.
SU00717
Figure 62. AC Testing Input/Output
V
LOAD
V
LOAD
+0.1V
V
LOAD
–0.1V
V
OH
–0.1V
V
OL
+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
V
OH
/V
OL
level occurs. I
OH
/I
OL
±20mA.
SU00718
Figure 63. Float Waveform
2 4 6 8 10 12 14 16 18
60
50
40
30
20
10
Frequency at XTAL1 (MHz, 6 clock mode)
I
CC
(mA)
89C660/662/664/668
MAXIMUM ACTIVE I
CC
TYPICAL ACTIVE I
CC
MAXIMUM IDLE
TYPICAL IDLE
SU01402
20
70
Figure 64. I
CC
vs. FREQ
Valid only within frequency specifications of the device under test
Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
84
t
RD
t
SU;STA
t
BUF
t
SU;STO
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
FD
t
RC
t
FC
t
HIGH
t
LOW
t
HD;STA
t
SU;DAT1
t
HD;DAT
t
SU;DAT2
t
SU;DAT3
START condition
repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
STOP condition
START or repeated START condition
SU00107A
Figure 65. Timing SI01 (I
2
C) Interface
V
CC
–0.5
0.45V
0.2V
CC
+0.9
0.2V
CC
–0.1
NOTE:
AC inputs during testing are driven at V
CC
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V
IH
min for a logic ‘1’ and V
IL
max for a logic ‘0’.
SU00010
Figure 66. AC Testing Input/Output
V
LOAD
V
LOAD
+0.1V
V
LOAD
–0.1V
V
OH
–0.1V
V
OL
+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V
OH
/V
OL
level occurs. I
OH
/I
OL
±20mA.
SU00011
Figure 67. Float Waveform

P89C664HBA/00,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 64KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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