AD7923SRUZ-EP

AD7923-EP Enhanced Product
Rev. 0 | Page 4 of 12
Parameter EP Version
1
Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
INH
0.7 × V
DRIVE
V min
Input Low Voltage, V
INL
0.3 × V
DRIVE
V max
Input Current, I
IN
±1 µA max Typ 10 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
2
10
pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
0.2 V min I
SOURCE
= 200 µA, AV
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4 V max I
SINK
= 200 µA
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance
2
1 pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
Binary
Coding bit set to 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max
POWER REQUIREMENTS
AV
DD
2.7/5.25 V min/max
V
DRIVE
2.7/5.25 V min/max
I
DD
Digital I/Ps = 0 V or V
DRIVE
During Conversion 2.7 mA max AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
2.0 mA max AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
Normal Mode (Static) 600 µA typ AV
DD
= 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) f
SAMPLE
= 200 kSPS 1.5 mA max AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
1.2 mA max AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
Using Auto Shutdown Mode f
SAMPLE
= 200 kSPS 900 µA typ AV
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS
650 µA typ AV
DD
= 2.7 V to 3.6 V, f
SAMPLE
= 200 kSPS
Auto Shutdown (Static) 0.5 µA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 µA max SCLK on or off (20 nA typ)
Power Dissipation
Normal Mode (Operational) f
SAMPLE
= 200 kSPS 7.5 mW max AV
DD
= 5 V, f
SCLK
= 20 MHz
3.6 mW max AV
DD
= 3 V, f
SCLK
= 20 MHz
Auto Shutdown (Static)
2.5
µW max
DD
1.5 µW max AV
DD
= 3 V
Full Shutdown Mode 2.5 µW max AV
DD
= 5 V
1.5 µW max AV
DD
= 3 V
1
Temperature range: EP Version: 55°C to +125°C.
2
Sample tested @ 25°C to ensure compliance.
Enhanced Product AD7923-EP
Rev. 0 | Page 5 of 12
TIMING SPECIFICATIONS
AV
DD
= 2.7 V to 5.25 V, V
DRIVE
AV
DD
, REF
IN
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Limit at T
MIN
, T
MAX
Parameter AV
DD
= 3 V AV
DD
= 5 V Unit Description
f
SCLK
2
10 10 kHz min
20 20 MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
t
QUIET
50 50 ns min
Minimum quiet time required between
CS
rising edge and start of next
conversion
t
2
10 10 ns min
CS
to SCLK set-up time
t
3
3
35 30 ns max
Delay from
CS
until DOUT three-state disabled
t
4
3
40 40 ns max Data access time after SCLK falling edge
t
5
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
10 10 ns min SCLK to DOUT valid hold time
t
8
4
15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance
t
9
10 10 ns min DIN set-up time prior to SCLK falling edge
t
10
5 5 ns min DIN hold time after SCLK falling edge
t
11
20 20 ns min
Sixteenth SCLK falling edge to
CS
high
t
12
1 1 µs max Power-Up time from full power-down/auto shutdown mode
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of AV
DD
) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
DRIVE
.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t
8
, is the true bus relinquish
time of the part and is independent of the bus loading.
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
10190-002
Figure 2. Load Circuit for Digital Output Timing Specification
AD7923-EP Enhanced Product
Rev. 0 | Page 6 of 12
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to AGND
−0.3 V to +7 V
V
DRIVE
to AGND
−0.3 V to AV
DD
+ 0.3 V
Analog Input Voltage to AGND 0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to AGND −0.3 V to +7 V
Digital Output Voltage to AGND −0.3 V to AV
DD
+ 0.3 V
REF
IN
to AGND
−0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except
Supplies
1
±10 mA
Operating Temperature Range(EP
Version)
55°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package, Power Dissipation 450 mW
θ
JA
Thermal Impedance
150.4°C/W (TSSOP)
θ
JC
Thermal Impedance
27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD 1.5 kV
1
Transient currents of up to 100 mA do not cause SCR latchup.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION

AD7923SRUZ-EP

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-BIT 4,Ch 200 Ksps ADC I.C.
Lifecycle:
New from this manufacturer.
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