MP7720 – 20W CLASS D MONO SINGLE ENDED AUDIO AMPLIFIER
MP7720 Rev. 2.1 www.MonolithicPower.com 8
1/22/2010 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
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Output Catch Diode, D1
D1 carries the current over the dead-time while
both MOSFET switches are off. Place D1
between pins 7 (SW) and 8 (PGND) to prevent
the voltage at SW from swinging excessively
below ground.
Input Modulator Capacitor, C3
C3 is used to set the amplifier switching
frequency and is typically on the order of a few
nanofarads. Place C3 as close to the differential
input pins (1 and 2) as possible to reduce
distortion and noise.
Reference Bypass Capacitor, C2
C2 filters the ½ V
DD
reference voltage at the
PIN input (pin 1). Place C2 as close to PIN as
possible to improve power supply rejection and
reduce distortion and noise at the output.
Use two separate ground planes, analog
ground (AGND) and power ground (PGND),
and connect the two grounds together at a
single point to prevent noise injection into the
amplifier input to reduce distortion. Power
components (C5, D1, C6 and C8) connect to
the power ground. The quiet analog
components (C2, C3, R2, and the input source
ground) connect to the analog ground.
Place the input and feedback resistors R1 and
R4 as close to the NIN input as possible. Make
sure that any traces carrying the switching node
(SW) voltage are separated far from any input
signal traces. If multiple amplifiers are used on
a single board, make sure that each channel is
physically separated to prevent crosstalk. If it is
required to run the SW trace near the input,
shield the input with a ground plane between
the traces. Make sure that all inductors used on
a single circuit board have the same orientation.
If multiple channels are used on a single board,
make sure that the power supply is routed from
the source to each channel individually, not
serially. This prevents channel-to-channel
coupling through the power supply input.
High V
DD
Operation
When operating at higher supply voltages,
special care must be taken to ensure that the
V
DD
level does not exceed the absolute
maximum supply rating of the IC. Power supply
pumping is of significant concern when
operating near the maximum supply voltage.
Supply pumping is an effect where the V
DD
voltage is “pumped up” to a higher potential
when charge from the output DC blocking
capacitor is transferred to the power supply rail
during switch transitions. The simplest way to
handle excess pumping is to increase the size
of the V
DD
main bulk capacitance such that the
extra charge will be absorbed by the increased
capacitance, with minimal supply increase.
One way to eliminate supply pumping
altogether is to use a different output
configuration circuit. Figure 2 shows such an
alternate configuration for connecting the
speaker load. With this configuration, one side
of the speaker load is connected directly to the
output of the LC filter, while the other side is
connected to the mid-point of a series
capacitor-divider (C26, C28). Both the LC filter
point and the mid point of the capacitor divider
will be at a DC bias level of ½ V
DD
, so the net
DC across the speaker is 0V
DC
. With the
speaker connected in this fashion, there is no
series capacitor to cause supply pumping, and
supply pumping is virtually eliminated. If the
output is connected in this way, however,
additional circuitry may be required to protect
the speaker from damage in the event of a
short circuit. Because both sides of the
speaker will be typically biased at ½ V
DD
, a
short-circuit to GND on the negative side of the
speaker load will result in a large DC current
through the load. For example, if V
DD
=24V and
R
L
=4Ω, there will be 12/4=3A of DC current
through the load. This current will be sustained
by the output FET stage of the IC as it will not
trigger the internal over-current protection
sense circuitry. A simple external sense circuit
will be required for those applications which
may experience an externally applied short
circuit under normal use. An example of such a
circuit is also shown in Figure 2.
