NCV4264−2C
www.onsemi.com
8
Circuit Description
The NCV4264−2C is is a low quiescent current
consumption LDO regulator. Its output stage supplies
100 mA with $2.0% output voltage accuracy.
Maximum dropout voltage is 500 mV at 100 mA load
current. It is internally protected against 45 V input
transients, input supply reversal, output overcurrent faults,
and excess die temperature. No external components are
required to enable these features.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V
OUT
) and drives the base of
a PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized.
Regulator Stability Considerations
The input capacitor C
IN
in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 W in series
with C
IN
. The output or compensation capacitor, C
OUT
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability. Tantalum, aluminum electrolytic, film, or
ceramic capacitors are all acceptable solutions, however,
attention must be paid to ESR constraints. The capacitor
manufacturer’s data sheet usually provides this
information. The value for the output capacitor C
OUT
shown in Figure 2 should work for most applications;
however, it is not necessarily the optimized solution.
Stability is guaranteed at values of C
OUT
w 10 mF, with an
ESR v 3.5 W for the 5.0 V Version with an ESR v 3.35 W
for the 3.3 V Version within the operating temperature
range. Actual limits are shown in a graph in the Typical
Performance Characteristics section.
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 3) is:
D(max)
+
ƪ
V
IN(max)
−V
OUT(min)
ƫ
*I
OUT(max)
) V
IN(max)
*I
(eq. 1
Where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and I
q
is the quiescent current the regulator
consumes at I
OUT(max)
. Once the value of P
D(max)
is known,
the maximum permissible value of R
q
JA
can be calculated:
P
qJA
+
(
150° C * T
A
)
P
D
(eq. 2)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
’s less than the calculated value in Equation 2 will
keep the die temperature below 150°C. In some cases, none
of the packages will be sufficient to dissipate the heat
generated by the IC, and an external heat sink will be
required. The current flow and voltages are shown in the
Measurement Circuit Diagram.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air. Each material in the heat flow path
between the IC and the outside environment will have a
thermal resistance. Like series electrical resistances, these
resistances are summed to determine the value of R
q
JA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(eq. 3)
Where:
R
q
JC
= the junction−to−case thermal resistance,
R
q
CS
= the case−to−heat sink thermal resistance, and
R
q
SA
= the heat sink−to−ambient thermal resistance.
R
q
JC
appears in the package section of the data sheet.
Like R
q
JA
, it too is a function of package type. R
q
CS
and
R
q
SA
are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heat sinking are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor Website.
